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Old 2nd December 2004, 08:37 AM   #1
PatPet is offline PatPet  Hong Kong
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Default AD1865N-K project launched

Hello,

After getting a few of these DAC chips in hand, now I decide to start the work.

Firstly, I'm going to use stripboard for the whole DAC. The reason is I lack experience in designing a pcb for this. I heard from somewhere that the cables/tracks carrying digital signals shall be kept short and thin, preventing noise pickups. I shall be eager to know if this is the case.

And right here is the draft of the structure of the DAC

1) signal selection, between AES/EBU XLR and SPDIF RCA
2) CS8414, DIP packaged
3) PLL reclocking, with Kwak clock
4) AD1865N-K, parallel or not to be tested and decided by my ears, balanced current output
5) Pass D1 I/V stage

flames or comments are welcomed
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Old 2nd December 2004, 01:07 PM   #2
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Default Re: AD1865N-K project launched

Quote:
Originally posted by PatPet

1) signal selection, between AES/EBU XLR and SPDIF RCA
I don't know how you plan on that, but I would suggest using Scientific Conversion input transformer with separate primaries that were specifically made for both inputs. This allows you the implementation without any additional switching circuitry (you might ground unused input maybe).

I just got those yesterday and they sound pretty good too.

http://www.scientificonversion.com/dualZo.html
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Old 2nd December 2004, 01:46 PM   #3
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Take a look at this:
http://www.ptsoundlab.com/secnumeriq...ac1865/dac.jpg

It is the digital part of an Autio Note DAC (the digital part is same for all of them).

The whole DIY guide can be found here (page is sometimes buggy).
http://www.ptsoundlab.com/secnumeriq...eroad1865n.htm
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Old 2nd December 2004, 01:59 PM   #4
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Kwak:

I don't really know the digital part of the DAC-s, but from my knowladge, the best NON-OS DAC-s use no jitter correction and reclocking, using a very simple receiver -> DAC signalpath.

I asked sometime at head-fi that how could I build myself a good NON-OS DAC designed for computer-as-a-source listening. The special about computer's soundcards is that they can use external sync signal - unlike CD transports, where they have to "lock-on" to the drive's continous dataflow.

Here is a quote from Glassman repleying to my question:

Quote:
if you're building your own DAC, the best thing you can do is to use some low jitter oscillator like Tent Clock or Kwak Clock inside your DAC and running S/PDIF output from your DAC to the card's digital input and letting the card synchronise to the incomming clock, that way you end up with absolutely jitter-free transmission and you can use any card with s/pdif in and out which has the capability to lock on external clock (pretty much every serious card)..
So, does it meen reclocking? I think it is just a precise clock inside the DAC, and a clean signalpath between the receiver and the DAC chip.
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Old 2nd December 2004, 02:08 PM   #5
PatPet is offline PatPet  Hong Kong
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Quote:
I don't know how you plan on that, but I would suggest using Scientific Conversion input transformer with separate primaries that were specifically made for both inputs. This allows you the implementation without any additional switching circuitry (you might ground unused input maybe).
How much do they cost?

I have some low-signal Omron relays in my box. If they are too expensive, I think I shall pick the relays.
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Old 2nd December 2004, 02:11 PM   #6
PatPet is offline PatPet  Hong Kong
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Quote:
http://www.ptsoundlab.com/secnumeri...dac1865/dac.jpg

It is the digital part of an Autio Note DAC (the digital part is same for all of them).

The whole DIY guide can be found here (page is sometimes buggy).
http://www.ptsoundlab.com/secnumeri...zeroad1865n.htm
Why do I see no sentences or words describing the circuit?

Any, the schematics are very useful. Thank you.
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Old 2nd December 2004, 02:13 PM   #7
PatPet is offline PatPet  Hong Kong
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And one more thing is that, for the digital signal cables connecting the board and the RCA/XLR connectors, is it absolutely to ensure they are short, or even thin?

What are the tolerences, if anyone has experience on this.
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Old 2nd December 2004, 02:42 PM   #8
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Quote:
Originally posted by PatPet


How much do they cost?

I have some low-signal Omron relays in my box. If they are too expensive, I think I shall pick the relays.
They are $15/pc. The advantage here is not only source selecting, but also improved interface, whith improved sonics.
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Old 4th December 2004, 01:51 PM   #9
philbyx is offline philbyx  France
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Hello

I'm planing too on a dac based on ad1865k-n (I have two of them), receiver cs8414 (I have two also, thank you Panda99).

I 'm thinking about digital part for the moment :

Transformer : why not a ethernet 10base5 transceiver transformer ?

Reclocking : all the reclocking I saw for the moment are reclocking bclk. In the case of the 1865, the important signal is the Latch on each chanel : LR, LL.

18 last bits of sdata, shifted by bclk in the register, go on the output and give the current when latch LR or LL goes low.

We can connect directly fsync on LR and fsync inverted on LL if the receiver cs8414 is in 18 bits mode lsb justified (mode 6). Realignement with shift registers in not necessary (it is necessary if I2S or msb justified).

Sdata goes directly on data left and data right (perhaps I will make balanced with two dac by chanel, sdata on one, sdata inverted on the other, 2's complement permits it...), bclk go to clk.

This is without reclocking.


If we want to reclock (anti jitter), we have to do it on LL and LE.

We have to make a super clock (in my case, a 33.8 Mhz, to send to my asus520 (the drive, for me) which have a poor ceramic oscillator on the MT1199 chip).

From this super stable clock, I will make a 2.88 Mhz Bclk which will clock D flip flop with fsync from the cs8414 on D to have a super LL and LR latches signal on Q and Qbar.


This is my project, and I wait for your advices...

Philippe
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Old 4th December 2004, 02:23 PM   #10
PatPet is offline PatPet  Hong Kong
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Hello Philbyx,

Okay, maybe I shall briefly explain the details of the digital part in my project.

Balanced mode is done as shown in the schematic below
The logic is done on the DATA line if I did not make a mistake.
Click the image to open in full size.

And the PLL filter is done on CLK, or SCK

Click the image to open in full size.

And for your reclocking plans, I'm afraid I encounter problems understanding. Maybe could I have some pictures or schematics of them, to make it clear?
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