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Old 16th July 2002, 11:42 AM   #11
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Default clock routing

Capslock,

Having but very limited experience in this area, can I pick your brain?

Why is a buffer between the clock and the DAC or whatever good to minimize jitter? Wouldn't there be a chance that the buffer itself generates jitter? After all, it is just another bunch of gates that have to switch states at some point on the rising/falling edge.

Thanks for any clarification.

Jan Didden
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Old 16th July 2002, 02:10 PM   #12
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Jan,

you are right that a buffer is bound to add some jitter. But let's consider how an oscillator works:
In many cases, there will be one or a few transistors that provide the gain that makes the crystal oscillate. The output is usually sinusoid which few DACs can accept and which is vulnerable to contamination if transmitted over a line due to its slow risetime. Therefore, one would use a comperator or logic gate to make this a square wave. This is already a buffer and would therefore work. This is in fact a configuration that one sees often enough. However, on its input this device sees a slowly changing signal and it has to decide when to switch. So a couple of V of noise on the input circuit that couple from the output capacitively or through the internal power supply rails would already result in several dozen ps jitter.
Hence it would be a better idea to load this "rectangularizing" gate as lightly as possible, i.e. with another buffer. It might even be a good idea to use several buffers to drive the DAC and the other non-critical parts of the board. These should not be within the same device lest nasties on the longer lines couple back into the buffer that drives the DAC.

For oscillators without a transistor , i.e. topologies where the gate (TTL, ECL, comparator) also drives the crystal, it is even more advisable not to load the output with anything else.

Although I haven't seen figures I would also expect a TTL gate to be much less jittery when driven from a high-slew-rate signal compared to something slower that is just within spec. The reason is again that the transition time trough the threshold region where noise may have an effect is much shorter for a fast signal. One should, however, limit overshoot that might cause the protection diodes to conduct by using a small series impedance.

Clear enough?

Eric
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Old 16th July 2002, 03:31 PM   #13
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Default Clock routing etc

Eric,

Yes, thanks, very helpfull.

As I said, this is not my area of expertise. I more or less assumed that the *squaring circuitry* would be included on the oscillator chip or whatever. Also, using a series resistor one would probably want to take a look at the capacitive load at the driven circuitry to avoid slowing down the rise times again, I guess.
Do you have any info on the shift of the switching point of a gate with time or with temperature? I know it varies from gate to gate, but does it vary over time/temperature for a particular gate?

Cheers, Jan Didden
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Old 16th July 2002, 04:02 PM   #14
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It's bound to vary except in temperature compensated gates such as the MC100 ECL series. But these would be slow changes which do not count as jitter.

The switching threshold is also a function of the supply voltage, so good decoupling is paramount.

Eric
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