Another clock idea for low jitter

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Hi,

basic idea is to average the width of n pulses.

For n = 10:

A clock is fed into 10 decimal counters which will stop at x = 1, 2, 3,4,5,6,7,8,9,10.

Each counters output x is used to gate the signal of the original clock to n another decimal ring counters, 10 stage each.
So that after power up the gated ring counters will start counting one after another.

Each output stage nr. 10 of those ring counters are fed together to a 10 input and gate.

This recovers the original clock signal.

_____________________________________________________

First ring counter starts counting on x = 1 and outputs a 1 after 10 clock cycles.

Second ring counter starts counting one cycle later on x = 2 and also outputs a 1 after 10 clock cycles.

Third ring counter starts counting on x = 3 and outputs a 1 after 10 clock cycles.

.....

Tenth ring counter starts counting on x = 10 and outputs a 1 after 10 clock cycles.


So each counter is delayed n cycles for n = 1 to 10.


Hope this is understandable.

if, over a periode of 10 cycles of the original clock there is a difference fom cycle to cycle, those differendes will be averaged.


Question is, if this counter and gate locics intoduce more jitter than they will reduce...

...anyway I dont believe in jitter :D

What will be improved theoretically is the width between the leading edges of the pulses.
 
Oh brother..........

Question is, if this counter and gate locics intoduce more jitter than they will reduce...

...anyway I dont believe in jitter

So........if you don't believe in jitter, then why are you asking?????

And if you don't believe in it, then you don't understand some of its root causes.

So, rock on, dude....................it is your $.

Jocko
 
Re: Oh brother..........

Jocko Homo said:


So........if you don't believe in jitter, then why are you asking?????

And if you don't believe in it, then you don't understand some of its root causes.

So, rock on, dude....................it is your $.

Jocko

It was a technical question about if it would help to reduce jitter.
Not if jitter is audible.

I dont believe in it because I have built Kwak clock and could not hear / measure any difference.

So, obviously you have no answer... why then post ???
 
I do have an answer.......

You may not want to hear it.

If you could not hear a difference, good or bad, with Elso's thingie, then it leads one to believe that you will not hear a difference with anything. Even if it has tons of gates in the clock generation circuitry.

If you could not measure a difference, then you need better test equipment. You can build your own, as I have done, to make the phase noise plots that I have posted. Not everyone has access to the fancy stuff that Signoro Tent has at work.

Lucky sod..........

Jocko
 
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