SONY SCD-XB770 Clock Mods

[kevinkr]

I recently acquired a sony scd-xb770 sacd player and am planning to install a new clock. The master clock is located on the audio board and runs at 11.2896MHz and clocks the 3 multibit delta sigma dacs directly (CXD9658N) and then is multiplied by 3 to 33.8688MHz for the DSD decoder IC (CXD2752R) The multiplier uses a 74LVU04A with a cap (22pF) and inductor (1uH) parallel resonant circuit connected directly across the input and output of each of 3 inverters, the inverters are then connected in series through small resistors. Obviously these filters must be tuned to the 3rd harmonic of the master clock. Does this circuit achieve a good lock to the master clock? I am a little sceptical actually.

What I am wondering is just how jitter prone is this clock multiplier circuit and given that I am not going to be using the dacs on the audio board much once I tap the dsd stream would it make more sense to divide a 33.8688MHz master clock down for the dacs?

Also does anyone have any information on the CXD2752R or the CXD9658N? Data sheets or/and crosses to non-proprietary part numbers?

See the schematic below:

[Elso Kwak]

Personally I would go for a low jitter 33.8688 MHz clock and divide by three with two D-type flip-flops. Horowitz page 513.

[kevinkr]

Hi Elso,
Thanks for your input, it pretty much confirms what I have been thinking might be the way to go.

I will use a two stage synchronous counter use an AND gate and AND the Q outputs. I initially thought to use JK type flip-flops, but noted that the 74HC74 D type clocks on the rising edge of the clock. Also what about the duty cycle of the divided clock?

So far what i am seeing with D type flip-flop does not look like a good clock source.

I will post something once the model seems to work correctly.

I don't have access to Horowitz & Hill so if you have a specific suggestion as to topology could you post here?

[kevinkr]

I got an implementation that looks like it works ok with 2 JK flip flops and an AND gate.. Produces 50% duty cycle clock output at 1/3 Fin. Will look at implementing with D type flip flops later. This is modeled of course.

[kevinkr]

Came up with d type implementation. Short of unexpected gate delays I should be able to get 50% duty cycle clock if that matters, otherwise edges are in right place on alternative output.
Circuit has been heavily simulated, does not seem to be particularly sensitive to clock speed within the allowed limits of the devices used. Note I have not yet built.. Will design pcb using smd passives and soic package logic.

And anyone have any comments. Thanks Kevin

[kva]

Hi

I am planning to sustitute the original clock in ..XB770 with LCaudio XO3. I have problems though getting the service manual to this player. Is there any chance you sharing this manual? It would be much appreciated!

Regards

[kevinkr]

Yes I would be happy to share the service manual with you.. I have it as a pdf file which is fairly large.. I can email it to you if you contact me privately off the board..

[kva]

Thank you!

Since you do not want allow emails from this forum I have contacted the adminstrator so I can email you from there.


Regards

kva

[Elso Kwak]

Hi kevinkr,
I would greatly appreciate receiving the PDF file of the servicemanual.
Unfortunately you have disabled the email button in your profile hence this post. Please contact me by hitting the email button below this post and I will reply with my email address capable accepting a large file. Sounds a bit complicated but is in order to keep the account free of spam.
Thanks in advance.

[Elso Kwak]

Originally posted by kevinkr
Came up with d type implementation. Short of unexpected gate delays I should be able to get 50% duty cycle clock if that matters, otherwise edges are in right place on alternative output.
Circuit has been heavily simulated, does not seem to be particularly sensitive to clock speed within the allowed limits of the devices used. Note I have not yet built.. Will design pcb using smd passives and soic package logic.

And anyone have any comments. Thanks Kevin

Hi Kevin,
VHC logic is giving less glare in digital circuits than AC or HC logic. The 50% duty cycle is probably not necessary as the player would also work with the 30%.