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Old 12th October 2004, 09:47 PM   #51
borges is offline borges  Norway
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Default Re: Thermal Tracking

Quote:
Originally posted by Elso Kwak


I have read somewhere that the idea was to get thermal tracking of the DAC and the resistor. If the DAC heats up the resistor also does.......I don't know squat if this makes sense or how the PCM1704 changes when heated up. Maybe it is all made up to be "interesting" to audiophiles.......This type of Vishay resistors have a very low Tempco. (about 1ppm)

So what can you do with two PCM1704s? Obviously, you can give one inverted data and go differential all the way to the output. But do you _really_ need perfect matching of gain and/or offset for that? With true differential signalling, a small signal-correlated common-mode signal (i.e. different gain in the + and - branches) should be accepted.

Or do you think they try in some way to add the output of two 24-bit converters to somehow gain a total resolution of 25 bits or more? Right now (on the second day of a cold and approaching bedtime) that's one of the few applications I can think of where you really need extreme matching.

Good night,
BÝrge
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Old 12th October 2004, 09:57 PM   #52
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Default Re: Re: Re: Re: Re: Optimizing a CS8414 + DF1704 + 4x PCM1704 DAC?

Quote:
Originally posted by Guido Tent


Hi

The only thing I can think of is increased jitter due to more noisy gates, but if you implement it correctly, it shouldn't be a problem

so I agree, more is not always worse

regards

That's not my bone of contention. What I am questioning is the notion that one decides how many chips to use based on some scale of audio 'goodness' and then sets about shoehorning the design into them.The logical conclusion of this ridiculous notion is that ASICs and FPGAs ought to be avoided like the plague. I often wonder how these chaps think digital audio devices format or demux data in the first place. By leprechaun, perhaps?
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Old 13th October 2004, 06:18 AM   #53
banana is offline banana  Hong Kong
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Default Re: Thermal Tracking

Quote:
Originally posted by Elso Kwak


I have read somewhere that the idea was to get thermal tracking of the DAC and the resistor. If the DAC heats up the resistor also does.......I don't know squat if this makes sense or how the PCM1704 changes when heated up. Maybe it is all made up to be "interesting" to audiophiles.......This type of Vishay resistors have a very low Tempco. (about 1ppm)
It reminds me of the build in I/V resistor in PCM63.

However, the real benefit of this build in I/V resistor approach was not mentioned in the datasheet....
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Old 14th October 2004, 03:14 AM   #54
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Default non-oversampling

Quote:
Originally posted by Hattori Hanzo

Sorry, I wasn't aware that the PCM1704 is not stereo and you will definitely need some glue logic. It also depends on the format that is available in your player. Most probably there's no finished and proofed concept but there are similar examples. One is here: Non Oversampling with PCM1704

Still, try to get around the input receiver and the DF once, maybe with another DAC and/or player...
He only says that the PCM1704 sounds better in non-os config than his tda-xyz converter. This is no miracle. He doesn't state non-os is better than os.
So I'm not very confident about this. In addition the shift register circuit is incomplete, yields phase shift etc.
He couldn't get stopped-clock operation running which is the only worth trying IMO, so he has no evaluation of it.

Did anyone really compare a stopped-clock non-os pcm1704 to os with a df11704?

Anyone has ideas how to implement something like the integer-oversampling ML does according to the article?

m.
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Old 14th October 2004, 07:35 AM   #55
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Default Re: non-oversampling

Quote:
Originally posted by dieringe

He only says that the PCM1704 sounds better in non-os config than his tda-xyz converter. This is no miracle. He doesn't state non-os is better than os.
So I'm not very confident about this. In addition the shift register circuit is incomplete, yields phase shift etc.
He couldn't get stopped-clock operation running which is the only worth trying IMO, so he has no evaluation of it.
Not sure why you think it is incomplete and definitely don't know where the phase shift idea comes from. Having tried both methods with the PCM63/1702 I could discern no difference between the two methods. They both varied wildly with the music played. FWIW the better NPC digital filters use the stopped clock method so perhaps there is something in the idea that there is an advantage in having the data static for a short while prior to conversion.
Quote:

Did anyone really compare a stopped-clock non-os pcm1704 to os with a df11704?
Herr Altmann, perhaps?

Quote:

Anyone has ideas how to implement something like the integer-oversampling ML does according to the article?

m.
What article?
Integer oversampling is exactly what the DF1704 does. All it means is you oversample by whole numbers. If you are prepared to decimate you can apply the same techniques to non-integer oversampling.
Oi, werner, any objections to the above ?
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Old 14th October 2004, 12:41 PM   #56
borges is offline borges  Norway
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Default Re: Re: non-oversampling

Quote:
Originally posted by dieringe

Did anyone really compare a stopped-clock non-os pcm1704 to os with a df11704?

Anyone has ideas how to implement something like the integer-oversampling ML does according to the article?

m.
What is stopped-clock non-os pcm1704? Does it mean that it receives indata at 44.1kHz and holds its output constant at 1/44100 seconds?

The way it's usually done is to take your 44.1/16 signal and insert 7 zeros between each original sample. Then you convolve that zero-inserted signal with a finite-duration, windowed sinc with 7 non-zero values between each zero (and the central one). The result of this is that each 8th sample is an original 16-bit number from your starting pcm signal and that between those, 7 derived (interpolated) samples are inserted. (You may choose to round those down to 24-bit number or any resolution you choose.) If your windowed sinc was infinitely long, the resulting digital signal contains the same information as the original signal. The benefit of oversampling is that input data is fed to your DAC at an 8 times higher rate. A PCM DAC like '63, '1702 and '1704 holds its analog output constant for one sampling period. The shorter the sampling period, the easier the rounding-off job required by the analog filter (because the output from the DAC is already greatly rounded off). Also, because intermediate signals are inserted, the differences between consecutive analog outputs are small.

In practicality, an 8x oversampler is built as three 2x oversamplers in series. That vastly simplifies the implementation. Because of this and because it is easy to divide a clock by 2^n, oversampling rates usually come as powers of two.

Oversampling involves no phase shift. It delays the data, but because the windowed sinc is symmetrical and of finite duration, all frequencies have the same delay.


Greetings,

BÝrge
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Old 14th October 2004, 01:04 PM   #57
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Default Re: Re: Re: non-oversampling

Quote:
Originally posted by borges
What is stopped-clock non-os pcm1704? Does it mean that it receives indata at 44.1kHz and holds its output constant at 1/44100 seconds?
forget it, I have to read more datasheets.
What I meant was holding the left channel while the right channel is loaded, but this is probably done anyway by the DAC?
But then I wouldn't need a shift register either - ?
I have no experience with this stuff, so I have lots of misunderstandings and better shut up.
I hoped there existed a concept I could try to understand...

m.
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Old 14th October 2004, 01:14 PM   #58
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Ok here is my stopped-clock idea:

For the left channel I OR the BCK with LRCK, feed the result into left PCM1704 BCK (this means BCK is stopped when right channel data is transferred), and OR the right channel with negative LRCK, feed into right PCM1704-BCK (or vice versa). Both channel DACs see all the SDATA but would ignore them when there BCK is stopped. Could something like this work?
m.

edit: ok, something must be done to WCLK also in a similar fashion...
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Old 14th October 2004, 02:46 PM   #59
borges is offline borges  Norway
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Martin,

you should do like I did with these matters:

1) Get a Xilinx or Altera FPGA demoboard
2) Learn Verilog or VHDL
3) Design any digital glue logic you can imagine

If you go for Verilog, I've got working code to read I2S and write to PCM1704 (and friends). My code is for polled bckl, which I get from the I2S of the CD drive or from the CS8414. (Should probably work with synchronous clocks too, but my SpartanIIe demoboard is a little low on clock resources.)

Maybe you can achieve non-os operation with simple glue logic. If you do, at least make sure you're using the upper 16 bits of the DAC. To do that, wouldn't you have to shift in 8 more zeroed lsbs after the 16 bits of data from the receiver?


Greetings,
BÝrge

Quote:
Originally posted by dieringe
Ok here is my stopped-clock idea:

For the left channel I OR the BCK with LRCK, feed the result into left PCM1704 BCK (this means BCK is stopped when right channel data is transferred), and OR the right channel with negative LRCK, feed into right PCM1704-BCK (or vice versa). Both channel DACs see all the SDATA but would ignore them when there BCK is stopped. Could something like this work?
m.

edit: ok, something must be done to WCLK also in a similar fashion...
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Old 14th October 2004, 04:38 PM   #60
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Quote:
Originally posted by dieringe
Ok here is my stopped-clock idea:

For the left channel I OR the BCK with LRCK, feed the result into left PCM1704 BCK (this means BCK is stopped when right channel data is transferred), and OR the right channel with negative LRCK, feed into right PCM1704-BCK (or vice versa). Both channel DACs see all the SDATA but would ignore them when there BCK is stopped. Could something like this work?
m.

edit: ok, something must be done to WCLK also in a similar fashion...

The logic you need depends on the CS8414 format you choose. Some formats make things easier than others.

Re demoboards and HDLs.
By all means get a development board, I have 4 and am designing a 5th but be aware the logic for stopped clock operation will fit in a XC9536 cpld that costs around 5 Euros. It is available in 44pin PLCC, a format relatively easy to work with whether SMD or socketed and schematic entry tools are freely available. A full blown FPGA development board on the other hand will cost anything from around 100Euros to the price of a small car.
As for HDLs,they are hardware DESCRIPTION languages. There is little point bothering with them until you fully understand the hardware you are describing.
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