Minimizing input-errors in opamp I/V. Help requested. - diyAudio
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Old 29th September 2004, 03:04 PM   #1
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Default Minimizing input-errors in opamp I/V. Help requested.

In a quest to optimise my opamp based I/V section, I read somewhere that ‘the impedance matching of both inputs of the opamp’ is required.
Browsing the internet for this toppic, I found the EDN article of Walt Jung, titled ‘Op-Amp audio – minimizing Input Errors’ (http://www.elecdesign.com/Articles/A...7206/7206.html).

The article defines 5 types of errors and defines my problem as ‘source-impedance-related errors. It discusses this topic in the application of the ‘non-inverting’ mode of operation, while my I/V-section is based on LM6181 operating in ‘inverting mode’ (feedback-loop to Vin(-) and Vin(+) to GND.


Is it worse the effort to match the input impedance of this I/V setup?

If so can the approach described by Walt Jung (for the ‘non-inverting’ opamp schems) be used ?

If not, why can’t that approach be used? And what should the be considered.


I post these questions here because I haven’t found much usefull on the net about this topic, also I will continue until I have the answers. (Isn't that what this forum is for?)

Thankx Henk
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Old 30th September 2004, 07:29 AM   #2
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Default Response by email from 'Janneman'

For those readers of the Thread, I think his respond is of interest and I therefor post it here.


--------------
Since your I/V is inverting, the + input is at virtual gnd, and, by the
opamp action, the - input is driven to this also. That is the reason
such an I/V is advantageous: it keeps the voltage on the DAC output
current terminal at gnd for lowest DAC distortion.

That also means that there is no common mode voltage (V+ - V- = 0) so
the distortion mechanism Walt explained does not happen.

Another issue is DC offset. Since the DC bias current of the two inputs
flows through the external source impedances, and since they ideally
are the same, there is no DC at the output (ideally) if the two source
impedances are equal. The source impedance seen by the V- input is the
impedance from V- to Vout (feedback resistor) // the DAC output
resistance which can be ignored as it is very high. So, using a resistor from V+
to gnd equal to the feedback resistance minimizes DC offset.

Lastly, you will want to keep both resistors as low as possible to
minimize thermal noise.

Jan Didden
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Old 18th October 2004, 04:34 AM   #3
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Hi Calimero,

I've been experimenting a lot with I to V converters - bipolar input OP are just not good enough! I settled with AD8066 which is one of the best in regards to input bias current and speed - probably the most important things in I to V converters. The resolution and speed I'm getting with 8066 is superb! Unfortunately, this OP needs attention because it can fry with more than 24V on power supply rails. Even with 24V (+ and - 12V DC) it runs very hot and needs additional cooling - I used heatsink compound and little copper heatsinks.

Another favourite of mine is AD826, but NOT as I to V converter...

Regards,
Nick
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Old 18th October 2004, 04:42 AM   #4
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This is very good artical on I to V conversion:
Attached Files
File Type: pdf i to v op.pdf (49.9 KB, 265 views)
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Old 18th October 2004, 07:42 AM   #5
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Hi Extreme_Boky,
Thankx for your response.

I have read in many threads here and in other articles on I/V conversion that opamps are not the best choice for I/V when trying to achieve the best results. Therefor I have the PCB and most of the parts ready waiting, of Rudolf's his 'Super pair i/v'. I hope to finish them before the end of the year and come to that same conclusion.

In the mean time I have implemented the useual mods in my my Proceed DAC (type DAP), to list a number:
- replaced OPA2604 in I/V with LM8161 (much better than opa627BP), with 47uF Elna caps on supply pins
- replaced OP2604 in output buffer with AD8066
- Power rails I/V and output buffer with ALW-regs (were LM317/LM337), increased voltage to 15V
- replaced AD1864N-K with AD1865N-K
- replaced and added decouple caps, near supply pins.
- power rails +5V and -5V of analog side of AD1865 with ALW-regs
- split supply of PMD100 and used OSCON 68uF on the pins
- implemented the power supply scheme described by Kuei Yang Wang in the thread 'OK so I modded my CD723 - but it's still mediocre' in the thread:
OK so I modded my CD723 - but it's still mediocre

And I am very happy with the BIG BIG improvements, however there always stays room for improvement. I'll get into the article you referred to, haven't seen that one yet.

Henk
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Old 23rd October 2004, 02:53 AM   #6
Oli is offline Oli  United Kingdom
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Default Dc bias. Question for Calimero

d.c. offset problem

Situation...

DAC- AD1865
IV conversion OPA627 (my preference)

Problem..

25mv of dc offset

I am trying find the solution to my offset problem and I have read your comments regarding balanced input impedances. I am aware that ideally the impedance should be equal on both inverting and non-inverting inputs. However, the input current of FET opamps (such as the OPA627) is very low- 5pA. I have calculated that the parallel equivalent of input impedance for the AD1856 (1.8K) and the feedback resistor (3k) equals 1.1k. This should give rise to 5.5nV of offset - insignificant! It would appear that balancing input impedances for FET opamps is not a problem for audio application. Indeed manufacturers do not bother with such configuarations on their data sheets. They simply tie the non-inverting input to ground.

Q. Have I missed anything?
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Old 26th October 2004, 01:25 AM   #7
Oli is offline Oli  United Kingdom
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Default Anyone?

Am I correct in my understanding of FET opamp d.c offset?
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Old 26th October 2004, 04:41 AM   #8
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Default Test the offset of the AD1865

Use 3k resistance conncet Iout and Ground to test the offset of the AD1865.
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Old 26th October 2004, 08:12 AM   #9
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Default DC offset problem.

Hi Oli,
I read about your offset-problems with the AD1865 in another thread.

Based on your line of reasoning that the bias currents are in the pA range for FET-opamps, I agree that your offset problem is not caused by the impedance difference of the opamp-inputs.

The impedance difference is nontheless a source of error (see article referred to by Extreme_Boky) also very small (in the range of 3-100 ppm).
Any error how small impacts the output signal. So thats why I am looking into this potential error source.

As such I understand this response doesn't solve your problem.
Haven't read all the info on your DC-offsett problem, can you tell me:
- what has been the reason of measuring the DC-offset and
- how did you perform the measurement

Regards Henk
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Old 26th October 2004, 08:35 AM   #10
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Default Re: Dc bias. Question for Calimero

Quote:
Originally posted by Oli
d.c. offset problem

Situation...

DAC- AD1865
IV conversion OPA627 (my preference)

Problem..

25mv of dc offset

I am trying find the solution to my offset problem and I have read your comments regarding balanced input impedances. I am aware that ideally the impedance should be equal on both inverting and non-inverting inputs. However, the input current of FET opamps (such as the OPA627) is very low- 5pA. I have calculated that the parallel equivalent of input impedance for the AD1856 (1.8K) and the feedback resistor (3k) equals 1.1k. This should give rise to 5.5nV of offset - insignificant! It would appear that balancing input impedances for FET opamps is not a problem for audio application. Indeed manufacturers do not bother with such configuarations on their data sheets. They simply tie the non-inverting input to ground.

Q. Have I missed anything?

Hi Oli,
As far as I remember the 25mv offset is typical for the AD1865. It was one of the reasons for me to try a balanced DAC with the AD1865. This way the offsets are cancelled omitting an output coupling capacitor. I don't think the offset is due to the opamp.
The TDA1543 has far larger offset! 1.6V in my DAC.
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