Address Decoding & Interfacing for DSP's

[fr0st]

I've started thinking seriously about my DSO project and I'm found some problems in designing the hardware.
This is my first DSP project so please bare with me
The dsp I'm using the the Ti TMS320VC5416 along with the CC studio (trial ).
I've only worked with PIC's before hand but know a little about proper buses (as oposed to the bit banging i'm used to).
My problem arises when I want to read the data from a 32k FIFO (16 bit data from a 120msps ADC) into the DSP's on chip memory via DMA or otherwise for FFT, interpolation etc. Basically, I don't know how to get the FIFO to act as a memory mapped device. I assume the best option would be a device (address decoder) that generates a strobe only when a certain address is outputed from the DSP so the FIFO can output the data onto the bus at the correct time. This would allow me to read the data off FIFO by polling the same memory location (Correct me if i'm wrong). Can anyone help me out with a 16 bit example (even an 8bit I can expand on).
The other problem is interfacing a graphic lcd to the DSP. I have the same addressing problem as the FIFO except even with the maximum number of waitstates on the bus the LCD is still too slow to be directly interfaced as a memory mapped perhibital.
Is there any way around this?
I though of may having some addressed GPIO pins for the task but I'm unsure of how to implement those aswell....

If any could help it would be very much appreciated
Thanks
Matt

[sek]

Hi,

which FIFO do you want to connect, and what type of (hardware and software) connection have you tried? If it has a serial interface, it certainly is no memory mapped device per se, you'd have to interface it manually then...

Also, have you considered using a timer interrupt, NOP wait counter or similar in order to achive the slow timing of the LCD (assuming the hardware connection works)? You could maybe just call a routine that waits for the right amount of DSP clock cycles before transmitting the next word, but then, you'd have to consider compiler optimization and hardware parallelization in the DSP...

I'm sure TI supplies some hints on those problems in their knowledge base. Don't just look for code examples prepared for your DSP. Look for examples in the older processor generations, too. Basically you don't have to wait for someone who invents running code for you setup, all you need is algorithms and their examples. I'm not too sure, but I remember having seen memory interfacing examples in the TMS320Cxx sections. There's stuff for days to study in there...

Hope this helps,
Sebastian.

[ingrast]

Originally posted by fr0st
... I assume the best option would be a device (address decoder) that generates a strobe only when a certain address is outputed from the DSP so the FIFO can output the data onto the bus at the correct time. This would allow me to read the data off FIFO by polling the same memory location

You are on the right track. Consider the FIFO as a regular peripheral (I/O port) to be read as usual. For this you must decode an address and generate a strobe (usually Output Enable) that is the Read strobe gated by the decoder. You have no means of addressing a particular word within the FIFO, must keep track by yourself where you are. FIFOs are no more than long wide shift registers where you only see input and output port.

...The other problem is interfacing a graphic lcd to the DSP. I have the same addressing problem as the FIFO except even with the maximum number of waitstates on the bus the LCD is still too slow to be directly interfaced as a memory mapped perhibital.

You may try buffering the LCD with an input tristate buffer and output latch. THis works the same as the former case, decode an I/O address (or several if required) and generate an Output Enable with the Read strobe, and a Clock for the latch with the Write strobe, both gated by the decoder.
This ensures stable signals for the LCD module for as long as you need under program control, may be software loops or timer interrupts (much better).

Rodolfo