jitter introduced by divider chips

[Sandor]

I have a transport + separate non-os dac combo with I2S connection.
Now I am going to put the master clock in the dac unit and slave it in the transport. Masterclock is 16.934400 MHz and the bitclock required by the dac chip (TDA1541A) is 2.822400 MHz. So I need to divide masterclock by six. The 74LS92 can do the job but:
HOW MUCH JITTER DOES THE DIVIDER INTRODUCE?
Best regards.

Paul

[OliverD]

I was about to ask the same question as I have a similar configuration.

Probably some logic families are better than others, and I suppose a very clean power supply is mandatory. Hard to predict the jitter if you don't know the environment the chip will work in.

Right now I'm digging out the LC clock schematics. If I remember correctly, Lars used some logic chips, too, and he did jitter measurements.

[OliverD]

Lars used the following output buffers:

LClock1 / LClock2: 74AC02
LClock XO / LClock XO2: 74AHC1G04
LClock XO3: 74LVC1G02

Ask Jocko and Elso.

[Guido Tent]

Originally posted by Sandor
I have a transport + separate non-os dac combo with I2S connection.
Now I am going to put the master clock in the dac unit and slave it in the transport. Masterclock is 16.934400 MHz and the bitclock required by the dac chip (TDA1541A) is 2.822400 MHz. So I need to divide masterclock by six. The 74LS92 can do the job but:
HOW MUCH JITTER DOES THE DIVIDER INTRODUCE?
Best regards.

Paul

Hi

The induced jitter depends on

- package size (inductance)
- logic family
- layout (external supply decoupling)
- supply noise (an inverter has only 6 dB PSRR)
- external circuitry like series resistors

Typically I'd suggest HC logic for the speed required, and use one package per divide step, preferably picogates. Ofcourse go for low noise, as with 1V/ns at the output you get 1 ps for each mV on te supply line......

NEVER use a string type divider like 393 here

You may consider reclocking the divided clock, just before it enters the 1541

Hope all helps

[Mark Hathaway]

Hello Guys,

Guido, what would you suggest for 24Mhz (and beyond) division and buffering?

Do you have any data to show us?


Regards,

Mark Hathaway

[Guido Tent]

Originally posted by Mark Hathaway
Hello Guys,

Guido, what would you suggest for 24Mhz (and beyond) division and buffering?

Do you have any data to show us?


Regards,

Mark Hathaway

Hi

You won't make it with HC so AC or ACT is the way to go. Go for SMD or single D flipflops like picogates

No data to share

cheers

[Sandor]

Thank you all for replies.

Guido:

The induced jitter depends on
...
- external circuitry like series resistors

series resistors increase jitter?

Typically I'd suggest HC logic for the speed required, and use one package per divide step, preferably picogates.

How can I simply implement a divider-by-six ?

NEVER use a string type divider like 393 here

What is a string divider? 7492 belongs to this family?

Regards.
Paul

[rfbrw]

Originally posted by Sandor

<snip>
How can I simply implement a divider-by-six ?
<snip>
Regards.
Paul

http://www.webmedia.pl/maciejza/zapl...c_vrds_25x.gif

The section in the linked schematic consisting of U103A & B (74HC112) forms a divide-by-three circuit. Connect the output of this circuit i.e Q (pin 9) of U103B to the clock input of a D type flip, e.g. a 74HC74, with its /Q output connected to its D input and the Q output will be the clock input divided by 2 giving an overall divide-by ratio of 6. The are probably better ways to do it, you could decode the Q outputs of a '163 counter (note uneven M/S ratio)but this is as good a place as any to start.

[Sandor]

Is it important for a dac clock to have a 50% duty cycle?

Paul

[Guido Tent]

Originally posted by Sandor
Is it important for a dac clock to have a 50% duty cycle?

Paul

Hi

Most DACs convert on either positive or negative slope, so no importance

regards