Paralleling up DAC chips

[Salar]

So, resurrecting this thread, BB/TI simply soldered together the current outputs of 4 PCM1704 DACS to feed one I/V stage?

http://focus.ti.com/lit/ug/sbau029/sbau029.pdf

They missed to draw a junction between the current outputs of the second and first pair PCM1702 in the schematics, (Page9 and Page10, close to the Iout symbol) did they miss something else in paralleling those dacs?
Would like to do this with 8 PCM1704 as well...
All the best,
Salar

[tritosine]

If you have fpga or dsp before the DA bloc you could give each one a slight offset, different for each chip, this supposed to deal with differential nonlinearity.

[jcx]

digital crossover would seem to be another method of usefully combining multiple DACs per channel

each DAC sees only a limited portion of the audio frequencies, reducing IMD


for parallel DACs with processing power you could also use "subtractive dither" - dither patterns in each DAC's drive that adds to zero in the summed output

[tritosine]

With the slight offset technique, 8x plain pcm1704 , might be easily better than 8x pcm1704K in ordinary parallel.

I dont see the need for dither with 24bit wordlength , it'd be useful to feed 16bit chips ( which are up to 20bit accurate) 24bit data, but 1704 should do without it , has no glitch anyway -with constant HF dither, the input is never 0 , obviously.

[jcx]

since subtacive dither ideally doesn't add to the output noise you can use very large amplitude

I would use large amplitude subtractive dither to linearize DNL - far above the lsb level in non signma-delta DACs

[Sebastiaan]

Look at how Accuphase do it. You can see their tricks if you go to their CD player PDF files.

With kind regards,
Bas

[Sebastiaan]

see here: http://www.accuphase.com/cat/dp-500_g.pdf

[rtd]

I recently buy an used HK HD760 which uses one PMD100 and 4xPCM1702.
Logic between PMD100 and DAC uses a "may be so called" parallel shifted DAC configuration (see link below)

http://www.neufgiga.com/n/50-17/shar...4de57549c7d68/

Is it really some kind of linear interpolation depicted in post 42 in this thread ?
Is it worth the case as opposed for instance making balanced dac with a 74HC86 ?

N.B : pmd100 is configured as 16 bit right justified and output 20 bits in 2's complement mode. DOL and DOR seems to be delay for 12 BCK cycle (I'm not sure)

[SoNic_real_one]

To me that is more a 2x oversampling and digital filtering - it doubles the number of samples, but "averages" the previous value with the current one....

[rtd]

Thx, what could the benefit of "averaging" this way ?
simple analog LPF which is the case and ...?

It could have been simplier to let the PMD100 oversample (8x in soft mode, mode they choose) and paralleling the DAC chips without delaying DATA (as depicted in PCM1702 evaluation board). But I guess there won't be many people who compared the two configuration.