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Paralleling up DAC chips
Paralleling up DAC chips
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Old 3rd August 2004, 06:20 AM   #71
rfbrw is offline rfbrw
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Originally posted by Bernhard

Is that schematic available somehow ?
From MJ 3/1993. The digital filter feeding the registers is the SAA7220P/B. Dacs are 4 PCM56 per channel. The registers are 74HC164.
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Old 3rd August 2004, 11:21 AM   #72
guido is offline guido  Netherlands
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Originally posted by guido

My two cent's:

The 6 '164 are cascaded as three 16 bit serial in/serial out registers.

They are then delaying the i2s with each time half a sample.
The DACs are then fed with:

dac1 current sample
dac2 delayed sample from half a sampleperiod ago
dac3 delayed sample from one sampleperiod ago
dac4 delayed sample from 1.5 sampleperiod ago.

Guess you also need glue logic to glue all together and create
the data for the four left and right channel dacs from i2s.

Result ~16 bit oversampling (?)

7220 output is i2s with 16 bit per channel, e.g. 7210 / CS8414 is 32 bit (16 unused).


Just lost 2 cents , the above is uhm

Anyway, thanks for posting. So the delay is a quarter of the sample, not half. Makes sence.. Result is still ~16 bit oversampling (?).


Edit: Is LE connected to WS, or do you need to create LE from it with some logic?
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Old 3rd August 2004, 12:11 PM   #73
Petter is offline Petter
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Originally posted by rfbrw

Not quite. The delay is half the sample time for every pair of dacs. It is functionally equivalent to linear interpolation and needs a reasonable number of samples to work well which is why it is usually preceded by an oversampling digital filter.

Are you indicating that one delays by:
2 dacs: Fs/2
4 dacs: Fs/4
6 dacs: Fs/8 or 6???
8 dacs: Fs/16 or 8???

Can I also assume that if 44.1 is running at 2X oversampling prior to this as an example - one would use 88.2 as Fs' and substitute Fs' for Fs in the above example?

I have been thinking about doing other variants of this to set up an "analog" low pass filter of a highly oversampled input by staggering either by a number of MCLK's. I have also considered adding gain (multiples - positive and negative) an setting up some sort of analog FIR current summing but do not have the expertise in digital filter design to be able to compute optimal setup.

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Old 4th August 2004, 12:34 AM   #74
rfbrw is offline rfbrw
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If you use a single LRCLK signal for all 4 dacs then LRCLK would have to run at 4Fs. With individual LRCLK signals, each dac runs at Fs but viewed from the output the combined 4 dacs run at 4Fs due to the staggering of LRCLK.
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Old 6th August 2004, 02:21 PM   #75
fumihiko is offline fumihiko  Japan
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anyone pallareling up delta-sigmaDAC?
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Old 8th August 2004, 05:24 PM   #76
catrafter is offline catrafter  United States
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What would be the result of paralleling up some PCM 1600Y multi-channel DACS in a receiver? Any sonic benifits?

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Old 8th August 2004, 06:34 PM   #77
jewilson is offline jewilson  United States
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So if we are playing a standard 44.1kHz CD we have these clock rates.

Fs 256= 11.2896 mhz
Fs 384= 16.9340 mhz
Fs 512= 22.5792 mhz
Fs 768= 33.8688 mhz

My questions are what or the methods of generation of the new clock. Then their is the issue of phase locking the old Fs new rate Fs to feed to the shift registers?

Of course I talking about keep the standard digital filter.

guess I am missing somthing here.

To make a real digital filter out of this would require much more work and then you want to be in a DSP.
Jim W.
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Old 9th August 2004, 12:31 AM   #78
rfbrw is offline rfbrw
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Originally posted by jewilson
guess I am missing somthing here.
Alas, a common event, it would seem.
Interesting figures, BTW. No idea where you got them from.
A digital filter, off-the-shelf or otherwise, precedes the shift registers. With an 8x filter L/R clock would be 352K8 and serial clock would be 11M2896, assuming 32 bit frames per channel and serial clock is continuous. For 4x hardware oversampling, L/R clock is passed through a 32 bit shift register, clocked by the 11M2896 serial clock, with taps at 8,16,24 and 32 serial clock cycles respectively and each tap is connected to only one of 4 parallel dacs. From the point of view of the composite dac made up of the 4 parallel dacs a L/R clock transistion occurs every 8 serial clock cycles i.e. at 4 times L/R clock.
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Old 7th February 2006, 04:21 AM   #79
PatPet is offline PatPet  Hong Kong
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One dumb question:

How would the waveform from each line looks like that in the data lines in an non-OS DAC? I mean are there pre-ringing issues with this register array?
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Old 7th February 2006, 05:57 AM   #80
rfbrw is offline rfbrw
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Ringing does not apply here. The data is unchanged.
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