Originally posted by jewilson
The next dac I build will have differetial dac. Anyway, the application notes I have seen only required you to inverter the data stream to the negative DAC.
That's debatable. I've made my case; you can make your choice.
http://www.diyaudio.com/forums/showthread.php?postid=426503#post426503
jbokelman,
Ok now you have gotten my attention! I need to go over the data but what you said in the other thread make good since.
if we call digital zero 0000,0000 and negative 0000,0001 your right it's not the same at all. Ok, so I need to look at this issue coding and bit value for the negative dac much closer than I have. I thought it was a simple clear cut deal since many companies have done it this way.
So have you implemented dac using 2's comp coding? I have some old Analog Devices books that have some good ifo on the subject. So now I am following what you’re talking about.
Ok now you have gotten my attention! I need to go over the data but what you said in the other thread make good since.
if we call digital zero 0000,0000 and negative 0000,0001 your right it's not the same at all. Ok, so I need to look at this issue coding and bit value for the negative dac much closer than I have. I thought it was a simple clear cut deal since many companies have done it this way.
So have you implemented dac using 2's comp coding? I have some old Analog Devices books that have some good ifo on the subject. So now I am following what you’re talking about.
I know a library that holds back issues of MJ but its a bit of a trek from Munich (St. Pancras, London) and it isn't open to the general public. I'd suggest having a look at one or two of the Wadia patents or the Teac and Denon schematics but on second thoughts they won't help very much as they all combine DSP oversampling filters or off-the-shelf oversampling filters with programmable logic.Originally posted by Bernhard
Is that schematic available somehow ?
Perhaps someone in the forum has a copy of the schematic?
scottnixon said:MJ had 2 or 3 articles in the 'Sidewinder' section. The only one I could find quickly was a weird one , that took I2S off of SAA7220 and fed 4 PCM56 per channel, through an array of 6 - 74HC164. This is in the March 1993 issue, page 200. I've tried some of the schemes years back (not this particular one as I didn't need the I2S conversion) and it was interesting. These are attempts at discrete versions of what Wadia was likely doing in DSP. French Curve / Digital Spline... what ever the marketing terms were 12 to 14 years ago
I had ever read this article,but...I have very difficult to understand Japanese.
IIRC,the DAC is to develop the sound quality of Marantz CD-99 LTD.
IIRC too,one DAC of the DIY match is the same topology in MJ 1996.
scottnixon said:MJ had 2 or 3 articles in the 'Sidewinder' section. The only one I could find quickly was a weird one , that took I2S off of SAA7220 and fed 4 PCM56 per channel, through an array of 6 - 74HC164. This is in the March 1993 issue, page 200. I've tried some of the schemes years back (not this particular one as I didn't need the I2S conversion) and it was interesting. These are attempts at discrete versions of what Wadia was likely doing in DSP. French Curve / Digital Spline... what ever the marketing terms were 12 to 14 years ago
EDIT !!!
For who read my reply: thought it was easy to reverse engineer.
But it is not (during a lunchbreak
). Might have another look at it, should be possible to reverse-engineer without schematic.Regards,
Hi,
My two cent's:
The 6 '164 are cascaded as three 16 bit serial in/serial out registers.
They are then delaying the i2s with each time half a sample.
The DACs are then fed with:
dac1 current sample
dac2 delayed sample from half a sampleperiod ago
dac3 delayed sample from one sampleperiod ago
dac4 delayed sample from 1.5 sampleperiod ago.
Guess you also need glue logic to glue all together and create
the data for the four left and right channel dacs from i2s.
Result ~16 bit oversampling (?)
7220 output is i2s with 16 bit per channel, e.g. 7210 / CS8414 is 32 bit (16 unused).
Regards,
My two cent's:
The 6 '164 are cascaded as three 16 bit serial in/serial out registers.
They are then delaying the i2s with each time half a sample.
The DACs are then fed with:
dac1 current sample
dac2 delayed sample from half a sampleperiod ago
dac3 delayed sample from one sampleperiod ago
dac4 delayed sample from 1.5 sampleperiod ago.
Guess you also need glue logic to glue all together and create
the data for the four left and right channel dacs from i2s.
Result ~16 bit oversampling (?)
7220 output is i2s with 16 bit per channel, e.g. 7210 / CS8414 is 32 bit (16 unused).
Regards,
rfbrw said:
Are you indicating that one delays by:
2 dacs: Fs/2
4 dacs: Fs/4
6 dacs: Fs/8 or 6???
8 dacs: Fs/16 or 8???
Can I also assume that if 44.1 is running at 2X oversampling prior to this as an example - one would use 88.2 as Fs' and substitute Fs' for Fs in the above example?
I have been thinking about doing other variants of this to set up an "analog" low pass filter of a highly oversampled input by staggering either by a number of MCLK's. I have also considered adding gain (multiples - positive and negative) an setting up some sort of analog FIR current summing but do not have the expertise in digital filter design to be able to compute optimal setup.
Petter
So if we are playing a standard 44.1kHz CD we have these clock rates.
Fs 256= 11.2896 mhz
Fs 384= 16.9340 mhz
Fs 512= 22.5792 mhz
Fs 768= 33.8688 mhz
My questions are what or the methods of generation of the new clock. Then their is the issue of phase locking the old Fs new rate Fs to feed to the shift registers?
Of course I talking about keep the standard digital filter.
guess I am missing somthing here.
To make a real digital filter out of this would require much more work and then you want to be in a DSP.
Fs 256= 11.2896 mhz
Fs 384= 16.9340 mhz
Fs 512= 22.5792 mhz
Fs 768= 33.8688 mhz
My questions are what or the methods of generation of the new clock. Then their is the issue of phase locking the old Fs new rate Fs to feed to the shift registers?
Of course I talking about keep the standard digital filter.
guess I am missing somthing here.
To make a real digital filter out of this would require much more work and then you want to be in a DSP.
Alas, a common event, it would seem.jewilson said:
Interesting figures, BTW. No idea where you got them from.
A digital filter, off-the-shelf or otherwise, precedes the shift registers. With an 8x filter L/R clock would be 352K8 and serial clock would be 11M2896, assuming 32 bit frames per channel and serial clock is continuous. For 4x hardware oversampling, L/R clock is passed through a 32 bit shift register, clocked by the 11M2896 serial clock, with taps at 8,16,24 and 32 serial clock cycles respectively and each tap is connected to only one of 4 parallel dacs. From the point of view of the composite dac made up of the 4 parallel dacs a L/R clock transistion occurs every 8 serial clock cycles i.e. at 4 times L/R clock.
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