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Old 17th July 2004, 01:10 PM   #1
MWP is offline MWP  Australia
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Question SRC4192 Use...

Hi all,

Im trying to work out how I need to use the SRC4192 resampler IC.

Im going to be setting up somthing like:
DIR1703 -> SRC4192 -> DAC

Does anyone have an schematic, etc they can put up as an example?
Ive been getting rather large headaches working out how to tie the three ICs together... in particular what input & output port modes the SRC4192 should be in, and where to get clocks from.

Thanks.
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Old 17th July 2004, 02:34 PM   #2
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Just a stab in the dark really. With the clocks I would imagine you would take the SCKO from the DIR1703 and input it directly to the SRC4192 RCKI pin. Then you select the same clock rate on both the DIR and the SRC via the relavent pins. Say you had SCF0 high and SCF1 low for a DIR of 256Fs. You would then select mode0,1 and 2 to either 1,1,0 or 1,1,1. depending on if you need input or output master mode? Appart from that I dont really know, its just a guess.

As I cannot see anywhere which indicates how you select the sample rate conversion it could be dependant on the clock selection

How to select what data to accept from the DIR and what data to give to the DAC looks simple enough. Im a little confused myself haha. But my next DAC was gonna be based around DIR1703 some upsampling device and then say four DAC chips in the output. PCM1794 in mono mode and paralleled or something.
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Old 17th July 2004, 02:52 PM   #3
gmarsh is offline gmarsh  Canada
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I've used the AD1896 chip, which is more or less identical.

From the DIR170x chip, you'll need to bring over I2S/LJ/whatever signals only - these attach to the BCKI, LRCKI and SDIN pins on the SRC.

The reference clock input (RCKI) is driven directly from your local oscillator, and the same oscillator that drives the DAC.

Pin strapping is used to determine the input/output formats, and to determine the output sampling rate of the SRC relative to the RCKI input.
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Old 17th July 2004, 03:23 PM   #4
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So if SCKO from the DIR would normally go to SCK on the DAC chip, you connect the SCKO from the DIR to the DAC & the SRC? and how do you select your upsampling etc? is it a standard resample everything to 192khz or is it a ratio thing?
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Old 18th July 2004, 02:28 AM   #5
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The DIR1703 has to be a master and it would probably be easier having the DAC as a master aswell.
You can disregard the master clock of the DIR1703 and only connect the Data, LR clock and bitclock to the ASRC's input port. On the DAC side, connect the Data, LR clock and bitclock to the ASRC's output port and your local oscillator (must be >= 128Fs which is probably your DAC MCLK aswell) to the ASRC's reference clock input. Both the input and output ports are in slave mode and your DAC must be the master.
The data format between the ASRC and DIR1703 can be of your choosing, they just both have to be set the same (16 bit right justified for cd?). You also have to set the output port format, as long as your DAC is set to the same thing it won't matter too much.
This way all data is upsampled and reclocked with a low jitter local oscillator instead of the DIR1703's 70ps one.
I think I explained that right....
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Old 18th July 2004, 03:10 PM   #6
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So in this situation do you still use a crystal with the DIR1703 or would it be better to drive the DIR from the accurate oscillator clock? I think it can work like this.

Im assuming that you would make something like the tent clock to feed the DAC and the ASRC.
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Old 18th July 2004, 03:48 PM   #7
BrianGT is offline BrianGT  United States
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The docucument for the SRC4192 eval board from TI has an example configuration:
http://focus.ti.com/lit/ug/sbau088/sbau088.pdf
It uses the CS8414.

--
Brian
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Old 18th July 2004, 05:50 PM   #8
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I d/l yet another pdf file
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Old 19th July 2004, 03:06 AM   #9
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I normal crystal should be fine in the DIR.
I'm not 100% sure but I'd imagine that the internal PLL (or oscillator) creates most of the jitter and not the crystal. The ASRC should eliminate any jitter on the input clock anyway, as long as the data in clocked in correctly and the frequency remains constant (I can't remember how accurate but it would be to strict, probably 100-200ppm ) the ASRC should be fine.
The DAC clock should be of high accuracy since it uses it as a time base for the output.
Please correct where wrong
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Old 19th July 2004, 04:38 AM   #10
jcx is offline jcx  United States
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Just a little reminder

There is no reason for ASRC in the reproduction chain, it simply encodes the sum of transport and ref clock jitter into the PCM words

The only legitimate use of ASRC is in the studio to merge live digital streams with multiple clock sources

The consumer can only assume that the PCM words on those shiny disks are meant to be reproduced at equal sampling times with the minimum jitter, Reclocking with a deep buffer (hard disk or even full track length ram as in xrcd mastering) and quality reference clock is the best “add on” option if a well executed (or tweaked) integrated player is for some reason considered unacceptable
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