Hello all.
I have a dead CDP-C505 sony that I want to try using as a DAC.
Is there a possible point on the board to which I might lift a pin and inject spdif? Or must I use some glue logic here?
I have no schematics on this board, and the only data I have is on the output opamp and the PCM56P dacs.
Could anyone help me with this?
I have a dead CDP-C505 sony that I want to try using as a DAC.
Is there a possible point on the board to which I might lift a pin and inject spdif? Or must I use some glue logic here?
I have no schematics on this board, and the only data I have is on the output opamp and the PCM56P dacs.
Could anyone help me with this?
Duo said:
The CXD2500Q is the DSP and the CXD2551P is the digital filter. If you wish to use it as a dac you will need to connect the output of a SPDIF receiver or some other source of audio data along with a source of masterclock. Pins 4,6,7 and 8 on the CXD2551P are the audio clock and data inputs.How easy or difficult it will be depends on the the source you use. I think the CXD2551P uses 48 bit data slots and you can confirm this by checking to see whether pin6 is connected to pin35 or pin37 on the CXD2500Q. Pin35 is bitclock for 48 bit slots and pin 37 is for 64 bit slots.
Once you can confirm what size data slots the CXD2551P uses and what input source you plan to use, I can give you a better idea of what is needed.
Okay, the pin 6 of the filter is connected to pin 35 on the DSP. So it must be 48 bit slot like you say.
My intention is to use it an audio DAC from spdif on a cdrom drive or typical cd transport.
The medium of connection is unimportant to me because I can implement optical, coax, or ttl without problems.
My intention is to use it an audio DAC from spdif on a cdrom drive or typical cd transport.
The medium of connection is unimportant to me because I can implement optical, coax, or ttl without problems.
Now you have a number of choices.
The first it to say its's too much bother and give up.
The second is to use an input receiver that supports the Sony format(fixed 48Fs bit/serial clock,Right/LSB justified data). There are some Sony devices but they are long out of production. The most available one is likely to be the TDA1373H but even that has been EOL'ed, if not discontinued. And it may need a microcontroller.
The third is to use any input receiver that can configure bit/serial clock and left/right clock as inputs,known as slave mode, and generate 48Fs bit/serial clock and Fs left/right clock from a new 384Fs clock. As none of the input receivers I am aware will allow right justified data in slave mode, the bit/serial clock to the input receiver will have to be a gated version of the 48Fs bit/serial clock limited to 16 cycles. Be aware that running the input receiver in slave mode with an unsynchronized source runs the risk of dropped or repeated samples.
The fourth is to use an asynchronous sample rate converter. In this case you would want one that has the option of limiting the output wordlength to 16bits. That limits you to the newer devices
like the AD189x series,AK412x series,CS8420 and the SRC419x series. But you will still need to generate the input clocks for the ASRC and you will probably still need to gate serial clock.
The fifth is to get a receiver that generates 384Fs system clock from the SPDIF data e.g. DIR1701/3 run it in master mode ( the DIR1701/3 only run in master mode) and use whatever logic is needed to interface the 64Fs clock and data generated to the 48Fs clock and data input of the CXD2551P. And unless you opt for programmable logic you are looking at a lot of TTL/CMOS packages.
Over to you.
The first it to say its's too much bother and give up.
The second is to use an input receiver that supports the Sony format(fixed 48Fs bit/serial clock,Right/LSB justified data). There are some Sony devices but they are long out of production. The most available one is likely to be the TDA1373H but even that has been EOL'ed, if not discontinued. And it may need a microcontroller.
The third is to use any input receiver that can configure bit/serial clock and left/right clock as inputs,known as slave mode, and generate 48Fs bit/serial clock and Fs left/right clock from a new 384Fs clock. As none of the input receivers I am aware will allow right justified data in slave mode, the bit/serial clock to the input receiver will have to be a gated version of the 48Fs bit/serial clock limited to 16 cycles. Be aware that running the input receiver in slave mode with an unsynchronized source runs the risk of dropped or repeated samples.
The fourth is to use an asynchronous sample rate converter. In this case you would want one that has the option of limiting the output wordlength to 16bits. That limits you to the newer devices
like the AD189x series,AK412x series,CS8420 and the SRC419x series. But you will still need to generate the input clocks for the ASRC and you will probably still need to gate serial clock.
The fifth is to get a receiver that generates 384Fs system clock from the SPDIF data e.g. DIR1701/3 run it in master mode ( the DIR1701/3 only run in master mode) and use whatever logic is needed to interface the 64Fs clock and data generated to the 48Fs clock and data input of the CXD2551P. And unless you opt for programmable logic you are looking at a lot of TTL/CMOS packages.
Over to you.
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