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Old 11th July 2004, 08:55 PM   #1
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Default VRDS10 digital output tweak

Hi!

I've an old 10 years VRDS10 and I'm changing some old caps for new one (power supply and coupling/decoupling caps first). I use it only as drive.

I've a question concerning the digital output.

I've found in the digital output circuit an 0.47UF + 100nF caps used to couple signal to the next stage. Do we have a way to improve this or not? What's the best? Just change the 0.47UF for a new one or another solution?

I've enclosed the schematic and wrote a red circle to show.

Thanks for your help and ideas.
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Old 12th July 2004, 07:18 AM   #2
lucpes is offline lucpes  Europe
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IMO it's safe to replace with a single 0.47uf film capacitor (WIMA MKP), check for the distance between the holes in the board before you buy it.
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Old 12th July 2004, 09:37 AM   #3
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The PCB est standard. Most the hole are 5mm. The problem is more W.

I'm not sure that 0,47UF exist for MKT or FKP series.

We can may be replace both 0.47UF and 0.1UF by an unique 0.1UF polypropylene caps? I'm thinking to MKP1837 serie from Wishay.
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Old 12th July 2004, 09:52 AM   #4
lucpes is offline lucpes  Europe
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Here's a good search engine: Farnell UK website search for 0.47uf

You want to know if you can replace 0.47uf+0.1uf with 1uf I suppose... Either 0.47uf alone or 1uf will do.
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Old 12th July 2004, 01:38 PM   #5
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The UK Farnell search engine is realy great. We don't have this in the French site (who is slow too).

Unfortunaly, a 0.47UF polypropylene caps from Wima MKP4 is realy too big to fit, and I'm not sure that this kind of caps is occurate to couple digital signal.

Wishay MKP1837 stop at 0.1uF and Wima FKP2 at 10nF.
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Old 12th July 2004, 02:26 PM   #6
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Hi

Forget about upgrading this path

Buy a new clock and apply reclocking at the digout of the CDX2500 processor

cheers
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Old 12th July 2004, 02:36 PM   #7
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Quote:
Originally posted by Guido Tent
Hi

Forget about upgrading this path

Buy a new clock and apply reclocking at the digout of the CDX2500 processor

cheers
I was thinking to you and your cristal at 26€... I was on your web this morning. Unfortunaly, I'm not quite ready to spend 150€ to offer a new complete clock board to my old VRDS10.

Just to know.

I've see on the XO3 version a "clock output". Is it something as a master clock? I have an DEQ2496 from Behringer. This unit have a master clock input. Does, the XO3 clock output will work with that?
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Old 12th July 2004, 02:54 PM   #8
A 8 is offline A 8  Sweden
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You don't need to spend 150€ to reclock spdif. You can build your own reclocker.
Get a flipflop, separate buffer and connect the current clock, you don't even need a board as it could be hardwired.
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Old 12th July 2004, 03:02 PM   #9
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Lightbulb Re: VRDS10 digital output tweak

Quote:
Originally posted by stef1777
Hi!

I've an old 10 years VRDS10 and I'm changing some old caps for new one (power supply and coupling/decoupling caps first). I use it only as drive.

I've a question concerning the digital output.

I've found in the digital output circuit an 0.47UF + 100nF caps used to couple signal to the next stage. Do we have a way to improve this or not? What's the best? Just change the 0.47UF for a new one or another solution?

I've enclosed the schematic and wrote a red circle to show.

Thanks for your help and ideas.
Hi Stef,
You can build this tranformerless interface. If you want a transformer it can be placed at the DAC-end before the comparator. Both the Scientific Conversions SC944-05 and the Pulse Engineering PE-65612 work well.
Any reclocking should be placed after the Digital Inputreceiver or in case of a digital filter after the latter as these are the main sources of jitter if you have mastered to control the reflections in the cable.
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Old 12th July 2004, 03:08 PM   #10
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Default SPDIF reclocker

Quote:
Originally posted by A 8
You don't need to spend 150€ to reclock spdif. You can build your own reclocker.
Get a flipflop, separate buffer and connect the current clock, you don't even need a board as it could be hardwired.

Hi A8,
My experiments did show that reclocking the SPDIF output with the masterclock of the CDP produced no improvement.
But of course YMMV...........
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