Hello everyone, (sorry for my English)
Well, this is my first post in the forum, but I think it wouldn't be the last
.
I actually study the possibility to upgrade a Pioneer digital processor, in fact upgrade the clock. It uses a Digital audio receiver Sanyo LC89055W to lock a PLL from the optical signal and then provides a 384.fs clock for digital filters.
Do someone have datasheet on this IC?
I'm also looking for datasheet or information on the IC PD7010A1 (I think manufacturer is Pioneer) . As it works in parallel with two SM5847AF digital filter, it must also be one.
I've forgotten to tell you, the digital processor is a 2x31 band equalizer and digital filter on 4 ways.
Thank you very much to help me in my quest.
Best regards
Cs
Well, this is my first post in the forum, but I think it wouldn't be the last
.I actually study the possibility to upgrade a Pioneer digital processor, in fact upgrade the clock. It uses a Digital audio receiver Sanyo LC89055W to lock a PLL from the optical signal and then provides a 384.fs clock for digital filters.
Do someone have datasheet on this IC?
I'm also looking for datasheet or information on the IC PD7010A1 (I think manufacturer is Pioneer) . As it works in parallel with two SM5847AF digital filter, it must also be one.
I've forgotten to tell you, the digital processor is a 2x31 band equalizer and digital filter on 4 ways.
Thank you very much to help me in my quest.
Best regards
Cs
So anyone to help me
.
Actually, it seems the 2 SM5847 worked with a 384.fs clock reference and same for the PD7010. This clock is coming out the LC89055, the digital receiver. As the DACs PCM1704 worked with a 192.fs BCK, I'm going to have to divide clock; that's not too difficult, but I also would have to keep phase beetween the divided clock and the out of SM5847s (I've got my idea).
It would be more simple for me to program by pin the PD7010 to work with a 192.fs clock as I know it's possible for the SM5847s.
So, if someone knows this IC, it would be great.
Cesium
.Actually, it seems the 2 SM5847 worked with a 384.fs clock reference and same for the PD7010. This clock is coming out the LC89055, the digital receiver. As the DACs PCM1704 worked with a 192.fs BCK, I'm going to have to divide clock; that's not too difficult, but I also would have to keep phase beetween the divided clock and the out of SM5847s (I've got my idea).
It would be more simple for me to program by pin the PD7010 to work with a 192.fs clock as I know it's possible for the SM5847s.
So, if someone knows this IC, it would be great.
Cesium
Cesium said:
I think it's a digital audio processor.
Cesium said:
The Bitclock is the Bitclock. And if you divide it, there are two bits at one clockcycle. Don't confuse it with MCLK ! The PCM1704 accepts BCLK up to 25MHz (96 [kHz fs] * 8 [Oversampling] * 32 [Bit Framelength])
I'm right, that the SM5847 is a flatpack with 44 pin ?
If so, Pin 5 outputs the Bitclock for your PCM1704.
http://www.npcamerica.com/Datasheets/SM5847.pdf
http://www-s.ti.com/sc/ds/pcm1704.pdf
Regards
Jobstens
Well, I'm going to explain what I would like to do.
Actually, my system is composed of a transport unit and FM receiver, and a processor unit opticaly linked.
Looking in manuals services, it seems that transport unit uses a 16,9344MHz (384.fs) clock to extract the CD's data, and a 11,2896MHz (256.fs) clock for the ADC (PCM1800) for a Sample Rate Converter (SM5849) and for a Digital Interface (TC9271). After this, the datas are transmied via optical link to the processor unit.
These datas are received by LC89055 (datasheet wanted) that seems to recover a 384.fs clock using its internal PLL. This recovery clock is then send to the 2 SM5847 digital filters and to the PD1710 (sort of digital filter I suppose, datasheet wanted). The 6 PCM1704 following these digital filters are configured to receive a 192.fs BCLK (44.1kHz x 24 x 8).
My goal is to upgrade the clock system to decrease as more as possible the jitter.
After studies of transport ICs, it seems easy to configure ADC, SRC and DIT to accept 384.fs clock (some pins to configure). So, 3 solutions appears:
1) get a good clock (LCAudio X03) at 384.fs, put it in the processor unit and distribute it to the SM5847s and the PD1710. Using a electrical connexion, send this clock to the transport unit to keep synchronisation and uses it for data extraction and for modified ICs.
2) Better solution but a little more complicated. Same as 1 for the electrical connexion to the transport and for the Digital filters, but divide the 384.fs clock to a 192.fs for the DACs. But I need to keep the same 192.fs that this one going out the SM5847 to keep phase with data. (I get one solution).
3) I have SM5847's datasheet, so I can modify pins to configure them in 192.fs clock instead of 384.fs. If I could get information on the mysterious PD1710 to make the same, I would just have to divide by 2 without need to keep the phase, more simple to me.
I'm waiting actually for the new equipments to replace my old one on which I'll try making the changes. Before, I'll make measurements to confirm my theory.
So, if someone has some infos on bolded ICs, it would be nice.
Best regards
Cesium.
Actually, my system is composed of a transport unit and FM receiver, and a processor unit opticaly linked.
Looking in manuals services, it seems that transport unit uses a 16,9344MHz (384.fs) clock to extract the CD's data, and a 11,2896MHz (256.fs) clock for the ADC (PCM1800) for a Sample Rate Converter (SM5849) and for a Digital Interface (TC9271). After this, the datas are transmied via optical link to the processor unit.
These datas are received by LC89055 (datasheet wanted) that seems to recover a 384.fs clock using its internal PLL. This recovery clock is then send to the 2 SM5847 digital filters and to the PD1710 (sort of digital filter I suppose, datasheet wanted). The 6 PCM1704 following these digital filters are configured to receive a 192.fs BCLK (44.1kHz x 24 x 8).
My goal is to upgrade the clock system to decrease as more as possible the jitter.
After studies of transport ICs, it seems easy to configure ADC, SRC and DIT to accept 384.fs clock (some pins to configure). So, 3 solutions appears:
1) get a good clock (LCAudio X03) at 384.fs, put it in the processor unit and distribute it to the SM5847s and the PD1710. Using a electrical connexion, send this clock to the transport unit to keep synchronisation and uses it for data extraction and for modified ICs.
2) Better solution but a little more complicated. Same as 1 for the electrical connexion to the transport and for the Digital filters, but divide the 384.fs clock to a 192.fs for the DACs. But I need to keep the same 192.fs that this one going out the SM5847 to keep phase with data. (I get one solution).
3) I have SM5847's datasheet, so I can modify pins to configure them in 192.fs clock instead of 384.fs. If I could get information on the mysterious PD1710
to make the same, I would just have to divide by 2 without need to keep the phase, more simple to me.I'm waiting actually for the new equipments to replace my old one on which I'll try making the changes. Before, I'll make measurements to confirm my theory.
So, if someone has some infos on bolded ICs, it would be nice.
Best regards
Cesium.
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