Regulators for digital circuits

[Peter Daniel]

I don't know about the guy from Germany but I tried Wima caps in crossover and they sounded better than Solen...I guess it all depends on taste.

As you know Digi-Key doesn't carry HFQ caps anymore and the only stock I have is 120u and 1000u. I settled on the latter.

 

[ftorres]

"Goudreau triplet",

I urge everyone to read this link and try the decoupling stratagy outlined by Pete Goudreau. The guy is super sharp and a have a paper he wrote on digtal decoupling that is one one my references on the subject.

Harry,

I have almost all of Pete Goudreau's posts concerning his struggle against TCP Dacs and UJB. I regularly reread them, and every time I'm amazed by his knowledge and physical background.

Do you know where I can find the paper you mention ? Is it available somewhere ?

While the regulators are important, the bypass caps are doing all the work above a few hundred KHz
The OSCON caps are great for electrolytics with COG ceramic bypass caps for the real high frequency stuff. We are talking currents in 10s of MHz here and a film cap is not going to cut it.

I used the "triplets" with more than benefit long ago on my "old" Dac, but without a multiple regulator approach. But concerning your OSCON/COG duet, I'm a little bit confused : COG SMT chips usually don't range over 1nF, and they become bulky as the value increase, as does their ESL. Do ultra low inductance 0612 chips exist in COG diel ? Is the OSCON good inough to avoid the "100-200 nF range" cap for intermediate frequencies bypassing ?

Moreover it seems to me that particular 'lytics and ceramic chips are to be chosen for their optimum combination of ESL/ESR and resulting impedance curve. Do you have some typical values in mind ?

 

[HarryHaller]

Pete Goudreau

I worked at Alcatel and knew Pete from a mutual friend. The paper is proprietary to Alcatel. Howard Johnsons book has a great chapter on decoupling caps and there is probably some stuff
on his website www.sigcon.com. I will look on the web for some app note locations. Electrolytic, stacked film and Surface Mount ceramic is probably the way to go.

http://www.faradnet.com/

http://www.sanyo.com/industrial/components/oscon_home.html

http://www.sigcon.com/Jennifer/Pubs/edn/pinductbypass.htm

http://www.sigcon.com/news/2_1.htm

http://www.sigcon.com/Jennifer/Pubs/news/5_3.htm

http://www.sigcon.com/Jennifer/Pubs/news/2_3.htm

H.H.

 

[dorkus]

where can you buy OSCON caps in the states? do they compare favorably to Panasonic FC?

 

[tiroth]

I have a question about the "Goudreau triplet". Does (physcially) stacking the bypass caps really have a significant advantage, other than being a clever way to retrofit an existing design? It seems to me that loop size is the same whether stacked or on the board, because vertical distance from ground matters too.

 

[HarryHaller]

Bypass caps for digital circuits

Mount the caps as close to the supply pins as possible. The small ceramics closest to the part.

http://www.sigcon.com./articles/straight/bypass.htm

http://www.glencoe.com/ps/ee/williamson/decoupling.html

H.H.

 

[ftorres]

Ultra low inductance SMT chips use 0612 packaging, which basically are of the same dimensions than their 1206 counterpart, but with the long side metallized. This allows to reduce the intrinsic inductance of the chip (400pH or less). It's then quite difficult to parallel several of them without adding pcb traces, and the only solution is stacking. A mere 100 mils trace can add up to 1 nH to the total inductance, and can destroy your efforts to lower this inductance...

 

[BrianL]

0612 vs 1206 SMT caps

I find it hard to believe that using 0612 caps for bypassing the
digital parts something like a CD player would have any
advantage over something like 1206 caps. The inductance
is only reduced slightly. Placement and dielectric type are
much more important. You can get 10nF (aka 0.01uF) C0G
caps in 1210 package and these should be just fine. I've
got some on my desk at work but haven't gotten around to
trying them yet.

And if you think this is just too much inductance, go for 0805
caps, though I doubt you'lll get more than 1nF in C0G dielectric.

 

[HarryHaller]

0612 vs 1206 SMT caps

I agree. The main point is to keep traces to caps short and fat to minimize parasistic inductance. I have used copper foil on top or the digital IC for this and and works great. You can get this tape from DigiKey. I believe it is made by 3M.

H.H.

 

[BrianL]

Oh, and I forgot to mention:

The ICs' lead frames and bond wires (i.e., the "pin" of the
IC and the stuff that connects it to the actual "chip" inside)
are far longer than the difference between the lengths
of 0612 and 1206 capacitors. This is true even for suface
mount ICs -- at least until we get to ones that are mere solder
bumps on the surface of the "chip" itself. (and when we're
at that point, we might as well forget about DIY with the
stuff)

The pins, lead frames and bond wires have far more inductance
than an extra 0.006" in choosing a 1206 cap over an 0612 cap.

Yes, the various copper foil tapes are made by 3M ("Scotch"
tape... ) and maybe others. And I do believe they're available
from Digi-Key.

 

[HarryHaller]

This is true even for suface mount

I don't know if that is true in all cases.....

H.H.

 

[ftorres]

An excerpt from Mr Goudreau's posts :

The best combination I have found to date that works by calculation,
simulation, measurement, and listening is as follows:

A Panasonic HFQ 'lytic, 120uF/25V paralleled with an AVX 0612
270nF/25V Z5U chip cap paralleled with an AVX 0612 10nF/50V X7R chip
cap. Note that these chip caps are 0612s, not 1206s. This yields a
nearly perfectly resitive driving point Z out to about 90MHz or so.
The residual inductance is on the order of 180pH which is swamped by
the internal parasitics of the bypassed device's leadframe and bond
wires. The 10nF should be mounted to the board first with the 270nF
on top so that inductance at high frequencies is minimized. This is a
very tedious task (having installed 28 sets of these on the DAC-1 I
can swear by that) but it can be done and provides a serious
improvement in performance by itself.

(whole post here)

A quick look at manufacturers' IBIS models gives a rough Pin to Die inductance (averaged on several chips) as follows :

• 
  DIL : 6-10 nH
  SOIC : 2.5-4 nH
  SSOP : 2.5-3.5 nH
  TSSOP : 2-3 nH

(Figures here just as a trend )

 

[HarryHaller]

Inductance

These look like reasonable typical numbers. Keep in mind the the parasitic inductances are additive and that trace indutance to the bypass cap is the easiest to minimize. Also interesting that surface mount has half the inductance of Dual Inline Packaging.
Thanks for the interesting numbers.

H.H.

 

[ftorres]

Triplet once more

Just a few things I tried.

I went on AVX web site to try to get ESR and ESL for their various ceramic chip. Found there a nice tool for getting impedance curves. Then I ran my simulator D) to see what happens.

The circuit is three paralleled caps : a 220nF/X7R/SMT, a 10nF/X7R/SMT and an electrolytic 100uF/10V/LowZ(Rubycon ZA). I added an extra inductance in series with the 'lytic to account for some PCB trace from it to the device it bypasses.The caps were modelled using a simple series RLC circuit (Cap= --ESR-Cap-ESL--), with no frequency dependance of ESR.

For a given Cap/Diel couple, AVX data show only a variation of ESL with the SMT package as follows :
-1206 1.3nH
-0805 1.0nH
-0612 0.6nH

Attached picture shows the impedance of the circuit for the three different packages. Capacitive behaviour at low frequencies, a mix of capacitive/inductive/resistive behaviours between 500k and 10Megs, and above all is inductive.

The 'lytic value acts on the LF part, its ESR fixes the plateau before the peak, and the intermediate region (nice peak, uh ?) is mainly (but not only) governed by the inductance of the 'lytic. I'm not sure of this value (used 10nH - but haven't been able to dig out some "real" values).

It seems here that one of the main points is to have a low inductance (not only low impedance) 'lytic. Impedance curves for them mostly stop at 20-30 MHz, where the inductive part is just beginning to act (OS-CON caps show about the same inductance at 20 MHz that other low Z brands...). Impedance values commonly found are at 100kHz, where all is capacitive and resistive. Knowing the internal structure (wound) of an electrolytic, the low inductance is not easy to achieve. A better way IMHO would be to // 'lytics, since inductance (and ESR) will be reduced and the Cap can be increased.

I'll try to get more realistic models/values for 'lytics' parameters (any hints/links here ?), and to find the best combination of SMT chips which will overlap nicely in the "disturbed" region

Flames welcome

 

[tiroth]

What about 0402 chip caps? These are only available in small values, but are small enough to actually place on top of SOIC pads. (provided Vdd and GND are adjacent)

 

[ftorres]

AVX states for an inductance of 0.8 nH for the 0402 chips, with a greater ESR. If 100nF and 10nF values can exist in such a package, you would obtain a curve between the red and he blue one. Adding a 1nF or smaller cap to the triplet will surely reduce the total inductance, but will add a ripple in the disturbed zone. But the (simulated) improvement is not amazing, and staking 10 SMT chips to reduce L is far beyond my skills... Anyone ?

 

[tvi]

SMT Speciality polymer electrolytic look good on paper

Rubycon ZL 100u/10V 480mA(rms) 0.15R
Panasonic UD 68u/8V 2A(rms) 0.018R

As the ESL of a cap is dictated by the shape, if you can find a ceramic the same size as the SP cap they should have the sames ESL.

Hope these help
<a href="http://www.electromarkinc.com/pdfs/pana061401.pdf">Panasonic SP Cap Catalogue PDF/1216k</a>
<a href="http://www.cornell-dubilier.com/surface.htm#Aluminum Electrolytic">CDE Surface Mount Capacitor Selector Guide </a>
<a href="http://www.cornell-dubilier.com/spa2.pdf">Performance Advantages for Solid Polymer Aluminum Capacitors PDF/195k</a>

Panasonic make (made?) a four terminal SP cap, but I can't find data on it anywhere at the moment.


Regards
James

 

[Ren Hoek]

SMT electolytics

Also try:

http://www.sanyo.com/industrial/components/poscap_home.html

Ren

 

[tiroth]

Part of my motivation for mentioning 0402 is that they are somewhat more common than 0612 package. It doesn't surprise me that they are not as good in terms of ESL, but the differences might equal out in trace savings for some (hand built) designs.

Thanks for the legwork on the ESL ftorres.

 

[ftorres]

Triplets again

Thanks for the hints/links. Were helpful to better understand some things.

tvi:
I found the ZA series to have a lower impedance (according to Rubycon). And your idea with ceramic chips made me think a lot.

Thus I wandered a lot on the net, and finally came upon something quite interesting : Murata makes high value (up to 100uF !) SMT ceramic caps, in 1206 or 1210 package. But much more interesting, these caps have a VERY low inductance, below 1nH ! Murata provides a free tool to get the characteristics of their chips (both capcitors and inductances).

By the way, I settled on a 22uF/10V 1210 chip, which looked fine for me, and back to Spice, I ran some sims, trying to get a nice overlapping in the 1MHz-100MHz region. I have to say now that I couldn't achieve this without adding another cap, so it's now a "quadruplet"

I compared three circuits, referenced according to attached curves:
-Goudreau : 100uF/10V/ZL // 270nF/0612 // 10nF/0612 (the original triplet)
-Murata : 22uF/10V/1210/ceramic // 220nF/0612 // 39nF/0612 // 10nF/0612
-MurataGoudreau : 100uF/10V/ZL // (Murata as above)

The characteristics of these caps are :
100uF : ESR=0.07, ESL=5.0nH
22uF : ESR=0.10, ESL=0.84nH
270nF : ESR=0.06, ESL=0.6nH
220nF : ESR=0.07, ESL=0.6nH
39nF : ESR=0.17, ESL=0.6nH
10nF : ESR=0.23, ESL=0.6nH

The electrolytic cap has an additional series inductance for its PCB trace to the other chips.

These values have been chosen after a limited optimization phase, which I not assume to be the best, but I ain't got enough time for that

The first plot is the impedance of the circuits. The use of the Murata chip (blue curves) shows a nice improvement mostly near 100kHz-5MHz. Compared to the original triplet (red curve), the chip has a lower capacitance, so a higher LF impedance, and its higher ESR levels up the plateau. This can be overcome by adding the 100uF cap, with a great benefit for the overall impedance (green curve). The use of a 220nF instead of a 270nF one helps to have a much nicer transition around 1MHz. The 39nF and 10nF caps work together to maintain the impedance at low level from 10 to 100 MHz, Above, the inductive part takes control

But we can look a bit differently at the curves. Plotting the only the inductive part of the impedance (Imaginary part divided by 2PI*F) in the HF region (second plot - on next post), shows a total inductance of 150pH (the 100uF has almost no effect here) for the quadruplet, and 300pH for the original triplet. Quite logical : we //ed more caps, thus we reduced the total inductance. But it has an interesting side effect : using V=Ldi/dt, this means twice less noise voltage for the same noise current variation...

You may think that paralleling 4 SMT caps (+ an electrolytic) might be overkill... Well, perhaps , but stacking 3 0612 near a 1210 can be doable. Give me a month, and I'll try (I'm lazy )

I can not speak for US, but in Europe 0612 caps are avalaible from Farnell, and the 22uF Murata can be obtained from Radiospares

Last thing : I'll try to get the same results with more commonly available 0805 or 0603 caps (no 0402, or I'll have to stop alcohol ), but I'm afraid we can not avoid the Murata...

Comments ? Help ?