Hello,
I'm interested in a simple hardware DAC tester that will create a 1kHz sine in a S/PDIF format. I'm looking for a TTL signal, the conversions I can do myself. I wonder if a small PIC or uC could create a 1kHz sine in S/PDIF format when powered up and output TTL so I can run it into jwb's DAC without having to use that big clunky dvd player I have. Anyone have done this before?
Thanks.
I'm interested in a simple hardware DAC tester that will create a 1kHz sine in a S/PDIF format. I'm looking for a TTL signal, the conversions I can do myself. I wonder if a small PIC or uC could create a 1kHz sine in S/PDIF format when powered up and output TTL so I can run it into jwb's DAC without having to use that big clunky dvd player I have. Anyone have done this before?
Thanks.
Take a decent soundcard with digital out, a PC, and the RMAA program from http://audio.rightmark.org/ .
Here's a test I did on mine: http://www.diyaudio.com/forums/showthread.php?s=&postid=429605
Here's a test I did on mine: http://www.diyaudio.com/forums/showthread.php?s=&postid=429605
till,
I want to generate a 1kHz sine with a 44.1kHz sampling frequency at 16 bits per sample. I have no idea what the data would look like for a 1kHz sine at a reasonable level enough to be heard through a line driver which is fed into an amplifier. A timing diagram would be a perfect start, but I don't know what the data would look like. Would you be able to help?
Thanks.
I want to generate a 1kHz sine with a 44.1kHz sampling frequency at 16 bits per sample. I have no idea what the data would look like for a 1kHz sine at a reasonable level enough to be heard through a line driver which is fed into an amplifier. A timing diagram would be a perfect start, but I don't know what the data would look like. Would you be able to help?
Thanks.
Well, after looking at it, I'll be choosing parts. Only part that I'm unsure of is the clock. What I plan on using to convert from i2s to S/PDIF is a DIT4096. Thing is, I need two extra clocks. First clock is the main clock, at 1.4112MHz which clocks the counter and binarey clock line. Second clock is The master clock to clock the DIT4096. I am not experienced in designing a PLL. Can I use a higher frequency crystal and use a counter to divide the clock? If I use a crystal that outputs a sine wave, I'll need to use some sort of IC to convert it to a square and divide the clock.
Thanks.
Thanks.
It's me again ...
you don't need to delay the data for 1 bit to use i2s. the DIT4096 accepts left justified data with 0 SCLK delay (see page 7 in the manual) ISYNC should be set to 1.
Build an osc. with 11.2896 MHz
This is MCLK to the DIT
This goes to the 4040 too.
On Q2 (Pin 6) you got your SCLK (1.4MHz),
Q3-Q6 from 4040 equals to Q0-Q3 in the EPROM circuit
Q7 from 4040 is Q4 = LRCK (44.1kHz)
LRCK goes to a second 4040 which generates Q5-Q13 (Output on the second 4040 = Q0 - Q8). With D1 you are reseting only the second 4040 - but you must inverting D1 or I do in a new binary (attached)
Could I remove all clarities ? ;-)
Regards
Jobstens
you don't need to delay the data for 1 bit to use i2s. the DIT4096 accepts left justified data with 0 SCLK delay (see page 7 in the manual) ISYNC should be set to 1.
Build an osc. with 11.2896 MHz
This is MCLK to the DIT
This goes to the 4040 too.
On Q2 (Pin 6) you got your SCLK (1.4MHz),
Q3-Q6 from 4040 equals to Q0-Q3 in the EPROM circuit
Q7 from 4040 is Q4 = LRCK (44.1kHz)
LRCK goes to a second 4040 which generates Q5-Q13 (Output on the second 4040 = Q0 - Q8). With D1 you are reseting only the second 4040 - but you must inverting D1 or I do in a new binary (attached)
Could I remove all clarities ? ;-)
Regards
Jobstens
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