Maybe this is the soloution:
1.) one DAC with normal data
2.) 2nd DAC with inverted data-signal in I2S
3.) a Resistor that adds (nearly) the Current of 1 LSB to the output of the 2nd DAC ...
3b.) Instead of the Resistor you could add a 3rd DAC that outputs permanently +1LSB
Or:
You are building caps in the signalpath ...
(The 1LSB is DC ...)
CYa
Jobstens
1.) one DAC with normal data
2.) 2nd DAC with inverted data-signal in I2S
3.) a Resistor that adds (nearly) the Current of 1 LSB to the output of the 2nd DAC ...
3b.) Instead of the Resistor you could add a 3rd DAC that outputs permanently +1LSB
Or:
You are building caps in the signalpath ...
(The 1LSB is DC ...)
CYa
Jobstens
CLARIFICATION
Going back to the 4-bit DAC example: With the sample sequence 2, 4, the output of the DAC will double from one sample to the next. The amount of change for that sample period is 6dB. The inverted samples are -3, -5. The output of the inverted DAC, for the same sample period, will change in the proportion 3:5 or 4.4dB. A signal that changes 4.4dB between two specific points in time is not the same shape as a signal that changes 6dB between the same two points. That difference is distortion.
You can figure out what happens with the sample sequence -2, -4.
Adding a bit to each sample in the digital domain results in distortion and I don’t think that distortion can be removed by adding a DC offset in the analog domain. Note: I make a distinction between adding a DC offset, after the fact, that is, after I/V conversion, verses biasing the DAC, which in effect, adds a 1-bit offset at the point of conversion, which is, arguably, still in the digital domain.
The point is, DAC designers, who simply invert the data stream to get an inverted output, rarely, if ever, bias the DAC so that a -1 digital input results in 0 analog output. As a consequence, their DACs have 6dB of additional distortion. Either they don’t know about it and don’t hear it or they know about it and don’t care.
Going back to the 4-bit DAC example: With the sample sequence 2, 4, the output of the DAC will double from one sample to the next. The amount of change for that sample period is 6dB. The inverted samples are -3, -5. The output of the inverted DAC, for the same sample period, will change in the proportion 3:5 or 4.4dB. A signal that changes 4.4dB between two specific points in time is not the same shape as a signal that changes 6dB between the same two points. That difference is distortion.
You can figure out what happens with the sample sequence -2, -4.
Adding a bit to each sample in the digital domain results in distortion and I don’t think that distortion can be removed by adding a DC offset in the analog domain. Note: I make a distinction between adding a DC offset, after the fact, that is, after I/V conversion, verses biasing the DAC, which in effect, adds a 1-bit offset at the point of conversion, which is, arguably, still in the digital domain.
The point is, DAC designers, who simply invert the data stream to get an inverted output, rarely, if ever, bias the DAC so that a -1 digital input results in 0 analog output. As a consequence, their DACs have 6dB of additional distortion. Either they don’t know about it and don’t hear it or they know about it and don’t care.
Inversion. The logic that performs the twos-complement works on all 16 data bits in parallel and has no influence on the clocks that control the DAC.
How does the serial inverter/adder know, at the moment it sees the LSB, what the following bits will be so, if necessary, the invert/adder can replace the maximum negative integer with the maximum positive integer?
Re: CLARIFICATION
One more (last?) try: 2-4: output is doubled, inverted samples are
-3 and -5. That output is doubled if you use -1 as reference:
-3 - -1 = -2
-5 - -1 = -4
Just try to picture it: normal DAC outputs a sinewave.
inverted DAC outputs the same sinewave, but the whole thing moved down 'one' LSB (mA,volt,whatever) on the Y axis (and the sine is inverted).
It is still a perfect sinewave...
jbokelman said:
One more (last?) try: 2-4: output is doubled, inverted samples are
-3 and -5. That output is doubled if you use -1 as reference:
-3 - -1 = -2
-5 - -1 = -4
Just try to picture it: normal DAC outputs a sinewave.
inverted DAC outputs the same sinewave, but the whole thing moved down 'one' LSB (mA,volt,whatever) on the Y axis (and the sine is inverted).
It is still a perfect sinewave...
jobstens said:Maybe this is the soloution:
1.) one DAC with normal data
2.) 2nd DAC with inverted data-signal in I2S
3.) a Resistor that adds (nearly) the Current of 1 LSB to the output of the 2nd DAC ...
3b.) Instead of the Resistor you could add a 3rd DAC that outputs permanently +1LSB
Or:
You are building caps in the signalpath ...
(The 1LSB is DC ...)
CYa
Jobstens
Re Point 2. Where does the inverted data come from?
jbokelman said:
The basic circuit is an inverter followed by a two-input serial adder with one input tied high. A loadable,bidirectional,parallel in,serial in,serial out shift register does the bit reversal.The D inputs on the shift register are tied to the max positive value. The Load input is asserted by a circuit that detects the max negative value.
All commercial DAC chips use ZERO as a reference. That’s what allows them to work properly with non-inverted data. If a DAC receiving inverted data is biased to a -1 reference, the output is not moved up or down by 1-bit as you claim. Except for being inverted, the output will appear normal in every way.
To invert the output of an audio DAC, you have several choices and they all involve creating a twos-complement of the original data.
1) Rip the music to a wave file. Replace every sample in the file with twos-complement data. Burn the modified file to a CD and play it.
2) In the DAC, add a parallel-out shift register and latch to capture each sample. Convert the sample to two-complement form. Use a parallel-in shift register transfer the data to the DAC chip.
3) In the DAC, invert the data stream (ones-complement). Bias the DAC chip so that a -1 digital input produces a 0 analog output.
Note: In applications using fixed-length binary data, the twos-complement of the maximum negative integer is still negative, not positive, and has to be dealt with as a special case. When carrying out choices 1 or 2, you have to recognize samples that contain the maximum negative integer and replace them with the maximum positive integer.
If the serial adder has one input tied high, it will add one to every bit. That’s not right. You add one to the LSB, only, and add the carry to the following bit. And what’s the advantage of the serial circuit? It seems you still need to hold the entire sample in a register so you can compare it to the maximum negative integer, replace it if necessary, and then shift the data out backwards into the DAC. Using a bi-directional shift register is cute but it makes the circuit difficult to pipe-line.
If you work at it, you might be able to come up with a usable circuit. I prefer the parallel approach: End of discussion.
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