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Old 4th May 2002, 06:40 PM   #11
tiroth is offline tiroth  United States
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Sorry for not thinking that through, I realize why latching is necessary.
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Old 18th May 2002, 07:55 PM   #12
tiroth is offline tiroth  United States
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Here is the current iteration of this circuit. The buffer is included so that the rise time of the distributed clock is slower and to ensure Tlh=Thl. A 74HC241 will be used; the LS part is simply for simulation. Any criticism on this setup?

The timing is actually a little tight for worst-case, but I think the 74F logic will be quite sufficient. Looking at the timing diagrams more closely, the latch could probably be omitted, but I think this would open you up to a host of potential timing issues.
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Old 18th May 2002, 07:56 PM   #13
tiroth is offline tiroth  United States
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Timing diagram for above. LRCK rises on the falling edge of BCK, as intended. I haven't found any datasheets that require a specific phase relationship between MCK and BCK/LRCK, so I believe this could be a good general purpose clock divider.
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Old 21st May 2002, 01:15 PM   #14
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Looks good to me, but I trust you for the different connections . Just don't forget to ground unused inputs on the 373. Speaking of that, did you have particular reason for chosing a 373 (level triggered) instead of a 374 (edge triggered) ?
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Old 21st May 2002, 02:52 PM   #15
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tiroth, can you give me your mail address ? (I can't help sending you a message from your web site....)
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Old 24th May 2002, 01:46 AM   #16
tiroth is offline tiroth  United States
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ftorres recently informed me via email that an 8 bit syncronous counter does in fact exist, the 74F269. This would be superior to the discrete solution.
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