Data and processing information arrangements

[eeka chu]

This is a really simple question, I've just forgotten the names of the arrangements I'm thinking about. And now, I can't find the answer with searches due to all the similar matches.

What is the name for an arrangement when data and it's processing information is held at the same address on the same bus? Like it is with Pentiums for example.

And then, when data and it's processing information are held on two seperate buses? I heard of this arrangement whilst I was reading about a PIC.

Sorry for it being kind of boring, but it's one of those things that just keeps my mind angry trying to remember!

[Gridstop]

This is really 'grey' area now... but what you're talking about are:

von Neumann architecture (data & instructions shared)
Harvard architecture (data & instructions separate)



These terms are sort of obsolete though, as all modern processors have separate L1 caches for instructions & data, although they share L2 cache & main memory.

[eeka chu]

Thanks Gridstop,

My brother is a lawyer and, in fact, actually delt with something to do with how L1 or L2 cache is delt with on a processor!

Can you suggest any good places to start reading about this kind of stuff specifically?

I've been reading a lot of sites recently about building your own MP3 player, but, since I have almost no knowledge of the more fundamental workings of processing, I'm kind of lost some times.

I understand decoding, clocking and such, my main problem is with memory addressing I think.

The kind of player I'm thinking of is composed of something like the VS1001 decoder, a memory system of some kind, like a compact flash card, and a simple processor.