Replace or Remove AD1893 in Teac VRDS 25X

[Fabian]

Hi everybody,

I’m trying to modify a Teac VRDS 25X. It uses the following chips:
CXD2545Q (CD-Decoder 16.9344MHz), AD1893 (ASRC, resamples to 48kHz with 18.432Mhz), SM5843, uPD65031 (signal conditioning for symmetrical D-A conversion, I guess), AD1862. The digital input receiver is a TDA1315H.

Beside other mods, I’d like to get rid of the AD1893. What shall I do. Replace it with AD1896 as there are replacement modules available? Or is it better to use no ASRC at all? I prefer a solution without ASRC, but this is probably more complex and I’m not sure how to do it.

Anyway, this is how the chips are connected right now:
The input format of the AD1893 (signal coming from CXD2545Q and TDA1315H is fed through some 74HC* and then goes to the ASRC) is set to serial input (16bit, I guess) / left-justified / no MSB delay / left-right clock timed. The output of the AD1893 is the same, except that word length is 24bit (16bit stuffed with zero?). This is described on page 1+18 in the datasheet.
The SM5843 is set to accept the same format (LR alternating / leading data / 20bit input) and data after LSB (bit 20) is ignored. Described on page 19 in SM5843 datasheet.

The main question is: what happens if I desolder AD1893 and directly connect BCK, LRCK and DATA (previously connected to the input of AD1893) to SM5843? The 20bit input of the SM5843 will be fed with 16bit data. Will the SM5843 fill the 4 last bits with zero? Will this work?

Of course I would also have to connect the 16.9344MHz clock to SM5843 and uPD65031. Does anybody have a datasheet of CXD2545Q or circuit diagram of Teac VRDS 25X (I’ve only got the circuit of ASRC-DF-DAC-Output-Stage)? This would be great help.

Well, that are many questions. Maybe some of you have already done something similar or have a little more experience with chip interfacing than I have, so thanks a lot for any advice,
Fabian

[rfbrw]

This probably won't help much but.......

[rfbrw]

A question and an answer.
Are the 74HC chips used to switch between the TDA1315 and CXD2545Q?
ALL 24bits out of the AD1893 are valid but if you bypass it the SM5843 can be set to accept 16bit data.

ray.

[Fabian]

Thanks for your postings Ray. In the meantime I recieved the whole circuit from Alexander. Many thanks again.
Now I see that some 74HC are used to convert Philips I2S to Sony format (invert LRCK and delay DATA by 7 bitcycles) and then the three lines (BCK, DATA, LRCK) from CXD2545Q or TDA1315H are switched by a 74HC4053 as you expected. After the switch LRCK is delayed by 8 bitcycles to make the format fit the input of AD1893 (convert from right justified to left justified).
If I remove the AD1893 I just have to remove the 74HC164 that delays LRCK after the switch and set the SM5843 to "LR alternating, trailing data, 16bit input." I guess this should work.

Now I have to think about the path of the 16.344Mhz clocks. Anyway, I'll keep you updated and it's very likely that I'll have some more questions

Fabian

[rfbrw]

Can you tell me what set of pins of the CXD2545Q uses for data, bclk and lrclk. Is it 45,46 & 47 or 48,49 & 50?
And are you sure it is the 16.9MHz clock that goes to the UPD65031 and not bclk?

ray

[Fabian]

Pin description for CXD2545Q:
LRCK = Pin45
DATA = Pin46
BCK = Pin47

In the original Teac VRDS 25X circuit the connections between SM5843 and uPD65031 consist of WCKO, BCKO, DOL, DOR and 18.432MHz clock from SM5843 Pin9 to uPD65031 Pin41.

Now that I want to remove the AD1893, I don't need the 18.432MHz clock anymore. The SM5843 and the uDP65031 need to be fed by the 16.9MHz of CXD2545Q or TDA1315H.

Fabian

[rfbrw]

According the Japanese datasheet for the CXD2545Q, it does not have an I2S mode and the data out on pins 45,46 & 47 is in what Sony and Philips refer to as the Sony format i.e. 48bit slots per L/R pair, BCLK/SCLK fixed at 48Fs and right or LSB -justified data with data valid on the rising edge of bitclock. With that in mind and the fact that the TDA1315 is an I2S only device, it is far more likely that the logic is converting the Sony format of the CXD2545Q to I2S rather than the other way round. It would also explain why Teac chose to use the 48bit slots when the 64bit slots were also available. Using the 48bit slots means one less HC164.
The delay after the switch seems very odd indeed in that it would make the data incompatible with any of the i/o formats accepted by the AD1893.

[Fabian]

Well, I don't have a datasheet of CXD2545Q, so I relied on the output description of all the CXD25** of which I found a datasheet at Sony datasheet search.
The outputs of every CXD25** are exactly as you described (48bit slots per L/R pair, BCLK/SCLK fixed at 48Fs and right or LSB -justified data with data valid on the rising edge of bitclock). This just to be sure we're talking of the same format.

The AD1893 is configured like I described in my first posting (see AD1893 datasheet p. 18, fig 24: BCLK_I normal mode, DATA IN no MSB delay mode).
I wonder why you think delaying LRCK by 8 bitcycles shouldn't work, because I can hear some nice music.

Philips I2S is converted to Sony format, I'm quite sure about this. You could hit the email button below and I'll send you the circuits if Alexander is in agreement.

You can have a look at the LRCK delay circuit at http://www.garmin.prv.pl/ -> zaplecze -> czytenlia. There you can see some more 74HC* logic between AD1893 and SM5843. Does anybody have an idea what this is for?

Fabian

P.S. Ray, are you tweaking a Teac yourself?

[Worboren]

6?¬6?!?buy this finetuned digital converter upgrade for Teac VRDS-25 in e-bay:

http://cgi.ebay.de/ws/eBayISAPI.dll?...sPageName=WDVW

"Austauschplatine für den werksseitig implementierten low-cost AD1893 Sample Rate Converter. Pinkkompatible Adapterplatine mit dem high-performance AD1896 Converter IC. Kompromisslose Ausführung mit Black Gate NX Kondensatoren. Es muß lediglich der AD1893 ausgelötet werden und die Adapterplatine eingelötet werden."

[rfbrw]

There is the possiblity of getting a VRDS-25? but I am not absolutely sure it is a 25x.
Anyway back to the what the logic does. Not that it matters much as it obviously works, its just a matter of what to call it but the mode pins on the AD1893 are set to Left justified data and that rules out the Sony format which is right justified.
The logic between the AD1893 and the SM5843 generates BCLK/SCLK and LRCLK at the new samplerate. That is how the AD1893 knows what samplerate to convert the incoming data to.

ray.