Tent clock waveform problems

[John Swenson]

I just put together a DDDAC kit which includes a Tent XO1 clock. When I look at the waveform coming out of the clock its a very bad squarewave. There is overshoot and undershoot on each edge of at least a volt. There is also at least one cycle of .5 volt ripple on top and bottom sections. The 5V supply is very clean, it has its own battery driven regulator.

With such a precision clock I expected a better waveform. Currently the output drives one HC load, is it supposed to drive a specific impedance? I checked the Tentlabs site and there is nothing about specific terminations.

It IS working, the DDDAC produces very nice sound, but I just can't believe the clock output is supposed to look like that.


John S.

[jean-paul]

Did you use 50 Ohm series resistor at the output as suggested ? And did you try another 5V supply for comparison ?

[ultranalog]

Of course you calibrated the probes of whatever measuring device you attached before you measured overshoot.

I found several philips data books on XO oscillators. From what I gather, Guido's XO has a fan-out of 10 (standard TTL load). Rise and fall time should be 5 ns.

If all the above check out, try a standard XO you would buy in any electronics store, and try another supply. This way you can uniquely determine which is the culprit.

[Guido Tent]

Originally posted by John Swenson
I just put together a DDDAC kit which includes a Tent XO1 clock. When I look at the waveform coming out of the clock its a very bad squarewave. There is overshoot and undershoot on each edge of at least a volt. There is also at least one cycle of .5 volt ripple on top and bottom sections. The 5V supply is very clean, it has its own battery driven regulator.

With such a precision clock I expected a better waveform. Currently the output drives one HC load, is it supposed to drive a specific impedance? I checked the Tentlabs site and there is nothing about specific terminations.

It IS working, the DDDAC produces very nice sound, but I just can't believe the clock output is supposed to look like that.


John S.

John,

If you apply a 47 ohm series resistor close to the output of the XO, a 50 ohm coax and 50 ohm input impedance of the scope, the waveform should be perfect, with a risetime close to 2 ns typically

If you measure it with a normal probe, at 1 M-ohm scope input, it looks uggly.

What you see on a scope is the result of the source (XO) and the interconnect (probes, whatever).

In addition, the extra wiring and loading on the DDDAC board may affect the waveshape too, as well as the power supply. Check, check and double check.

Let me know how you proceed

regards

[John Swenson]

Thanks Guido. On the board there is about 3/4 inch between the XO and the receiving chip, do I need to put the series resistor between them? If yes is that sufficient or do I need a terminating resistor at the load? Or no series resistor and a terminating resistor?

Thanks for input on this.

The circuit actually is working but I'm wondering if its working to its fullest potential as is.

Thanks,

John S.

[Guido Tent]

Originally posted by John Swenson
Thanks Guido. On the board there is about 3/4 inch between the XO and the receiving chip, do I need to put the series resistor between them? If yes is that sufficient or do I need a terminating resistor at the load? Or no series resistor and a terminating resistor?

Thanks for input on this.

The circuit actually is working but I'm wondering if its working to its fullest potential as is.

Thanks,

John S.

John

I'd suggest a 47 ohm series R close to the XO

termination not required

Does the receiving chip has resistors at its' outputs ?

Does the XO measure correctly when probed correctly ?

regards

[ThorstenL]

Konnichiwa Tent San,

A quick question or two, if I may. I'm currently implementing the Tent Clock in a commercial Mod Package. Using Sanyo Os-Con's and a very low inductance stacked film capacitor bypass capacitor plus a modest value series resistor (27R) with some ferrite beads on the lead from a reasonably clean 5V supply works quite well and sounds rather good (and yes, I use a 47R5 build out resistor) .

However, two concerns, first the input driven by the Clock is a 3.3V Decoder IC, currently driven without level shifter. I'm sure reducing the input overdrive will help the overall performance.

Now I can get some inexpensive, rather high value resistor shaped chokes that would make a great substitution for the resistor and would provide a serious lowpass (>-8db @ 50Hz) by using minimal numbers of components (22mH Choke, 33uF Os-Con with bypass, a few ferrite beads).

The downside is a pretty high DCR with my preferred part, which would drop the supply voltage to the Xo appreciably below the required 5V. In some ways that would seem desirable, as it would reduce the overdrive to the input of the Decoder chip.

So, any comments? Does the XO work at lower supply voltages without significant performance degradation? Otherwise, should I worry about 5V vs 3.3V logic?

Sayonara

[Guido Tent]

Originally posted by Kuei Yang Wang
Konnichiwa Tent San,

A quick question or two, if I may. I'm currently implementing the Tent Clock in a commercial Mod Package. Using Sanyo Os-Con's and a very low inductance stacked film capacitor bypass capacitor plus a modest value series resistor (27R) with some ferrite beads on the lead from a reasonably clean 5V supply works quite well and sounds rather good (and yes, I use a 47R5 build out resistor) .

However, two concerns, first the input driven by the Clock is a 3.3V Decoder IC, currently driven without level shifter. I'm sure reducing the input overdrive will help the overall performance.

Now I can get some inexpensive, rather high value resistor shaped chokes that would make a great substitution for the resistor and would provide a serious lowpass (>-8db @ 50Hz) by using minimal numbers of components (22mH Choke, 33uF Os-Con with bypass, a few ferrite beads).

The downside is a pretty high DCR with my preferred part, which would drop the supply voltage to the Xo appreciably below the required 5V. In some ways that would seem desirable, as it would reduce the overdrive to the input of the Decoder chip.

So, any comments? Does the XO work at lower supply voltages without significant performance degradation? Otherwise, should I worry about 5V vs 3.3V logic?

Sayonara

Sayonara-san,

Thanks for the mail

If the logic runs at 3V3, I use a 100 ohm to 220 ohm resistive divider, instead of the normal 47 ohm output resistor.

The choke is OK, take care the circuit is reasonably well damped

I am looking into the jitter performance as function of the supply voltage

By the way, my XO contains an on board decoupling......

cheers

[ThorstenL]

Konnichiwa,

Originally posted by Guido Tent
If the logic runs at 3V3, I use a 100 ohm to 220 ohm resistive divider, instead of the normal 47 ohm output resistor.

Will do.

Originally posted by Guido Tent
The choke is OK, take care the circuit is reasonably well damped

Originally posted by Guido Tent
By the way, my XO contains an on board decoupling......

I have attached the Circuit I used to simulate two ferrite beads and the choke (per datasheet) plus the 33uF Sanyo Os-Con and 10nF stacked film. All is soldered together very tightly, so the parasitics should be close.

As can be seen, any high order/frequency noise out of the supply is well suppressed, 18db @ 300Hz, 48db @ 3KHz and > 90db @ 30KHz to around 700KHz with still > 40db @ 10KHz. The one core resonance observable is that of the choke itself.

Do you think I got this close? How much capacitance with what sort of ESL & ESR is inside the clock (if you can/want to mention it of course)?

I personally simply prefer using passive circuitry to do dirty jobs, it tends to be much easier to get this right than regulators.

Originally posted by Guido Tent
I am looking into the jitter performance as function of the supply voltage

I'd be very interested in the results.

Sayonara

[Elso Kwak]

Originally posted by Kuei Yang Wang
Konnichiwa,

Will do.





I have attached the Circuit I used to simulate two ferrite beads and the choke (per datasheet) plus the 33uF Sanyo Os-Con and 10nF stacked film. All is soldered together very tightly, so the parasitics should be close.

As can be seen, any high order/frequency noise out of the supply is well suppressed, 18db @ 300Hz, 48db @ 3KHz and > 90db @ 30KHz to around 700KHz with still > 40db @ 10KHz. The one core resonance observable is that of the choke itself.

Do you think I got this close? How much capacitance with what sort of ESL & ESR is inside the clock (if you can/want to mention it of course)?

I personally simply prefer using passive circuitry to do dirty jobs, it tends to be much easier to get this right than regulators.



I'd be very interested in the results.

Sayonara

Goedeavond,
Is that 180pF a realistic value?
I have found that a combination of passive (Pi-filter) and active filtering (good regulator) gives the best result sonically.
Tot ziens,