thanks T, I wonder what all that expensive transformers will do in my friend's AD1875 DAC, never heard one and like to hear side by side with TDA1541.
and that pcb layout I've sent to you is now singing, you're right it needs re-layout 🙂, waiting for marce's excersice & further hints here ..
and that pcb layout I've sent to you is now singing, you're right it needs re-layout 🙂, waiting for marce's excersice & further hints here ..
I am using a pair of Sowter 9545 transformers with a 56R load resistor (paralled tda1541a) and nos operation.
I like the results very much but the sound is influenced by the input impedance of the preamp the transformers are connected to since this is reflected back to the primary.
The best result is with the standard input config of my Quad 34 preamp. (39k in series with 680n to the inverting input of a op2604))
I did try modifying it but the results were not as good. Maybe if I'd played around with it more I'd have had a better result..
The main reason for using these expensive transformers is for dual differential working which is a 'work in progress'.
Hi, yes I've read your dual dac differential posts, my friend is using lundahl, hopefully in September or so I'll have the chance 🙂, I've tried 22 to 100R for my single dac, 33R shinkoh is best to my hearing, maybe your parallel tda might need 15R, love to see your progress on dual differential..
Once I have the differential operation working I will experiment with the load resistors. (hopefully this week)
My previous tda1541a dac (dual differential) used an "analog" star ground emanating from Agnd for all local decoupling (to gnd) on the bottom of the pcb (ceramic // polymer in case D on the supplies and SMR (through hole) for averaging of the switched currents). Supply decoupling is placed on both sides of the pcb directly beneath the tda1541a for minimized loop areas.
A few further details are I did use stacked tl431:s and decoupling between -5 and -15V , DEM reclocking (as per Htp) but no i2s attenuation bar a slight lowpass filter and of course the data is split into left and right so each dac is run truly differentially (bar the missing lsb from not doing proper 2s complement inversion).
I have still to see the internal schematic of the 1541a but I have made this layout sketch by redrawing the layout I used based on the comments made by TL in this thread. I have only used two layers here so some cutting of planes are inevitable.
Comments? (Dgnd on top, Agnd beneath pin 4-5 are the common connection, Tl431 shunts, the rest should be recognizable by anyone who have starred at a 1541a for long enough)
A few further details are I did use stacked tl431:s and decoupling between -5 and -15V , DEM reclocking (as per Htp) but no i2s attenuation bar a slight lowpass filter and of course the data is split into left and right so each dac is run truly differentially (bar the missing lsb from not doing proper 2s complement inversion).
I have still to see the internal schematic of the 1541a but I have made this layout sketch by redrawing the layout I used based on the comments made by TL in this thread. I have only used two layers here so some cutting of planes are inevitable.
Comments? (Dgnd on top, Agnd beneath pin 4-5 are the common connection, Tl431 shunts, the rest should be recognizable by anyone who have starred at a 1541a for long enough)
Attachments
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Regular aluminum, you can see the dac here:
http://www.diyaudio.com/forums/digi...her-tda1541a-based-dac-dual-differential.html
Looks very similar to my layout. Seems you have done 'everything right' as far as I could distill from the other threads and HtP's comments. Curious what more experienced developers think.
I do recall, however, that the general consensus on tl431 is not very positive... however better than the 78xx regs. Do you have space for discrete shunt regs (e.g. salas shunt) ?
I do recall, however, that the general consensus on tl431 is not very positive... however better than the 78xx regs. Do you have space for discrete shunt regs (e.g. salas shunt) ?
Ah, so this mode also accepts data on both pins 3 and 4 or how else are you handling the inverted data?
Yeah, I'm curios for more input but a going for a 4-layer PCB would open up quite a few more degrees of freedom.
I'm not aware of that particular shunt but its my experience the tl431 can be made to function very well.
>> Batteryman
I used a 64bit deep shift register to delay the data and some logic to sort the data into L/L- and R/R- frames. Pedja Rogic posted a similar circuit that does this a few years back.
I'm not aware of that particular shunt but its my experience the tl431 can be made to function very well.
>> Batteryman
I used a 64bit deep shift register to delay the data and some logic to sort the data into L/L- and R/R- frames. Pedja Rogic posted a similar circuit that does this a few years back.
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I used to have a setup like;
Salas shunt --> tl431 --> tda1541
Removing the tl431 gave great improvements. At this time I didnt have a scope so I couldnt see whether this was due to oscillations between the 2 regs.
Salas shunt --> tl431 --> tda1541
Removing the tl431 gave great improvements. At this time I didnt have a scope so I couldnt see whether this was due to oscillations between the 2 regs.
Hi,
The Salas shunt should have less dynamic impedance in the audio range and less noise. It seems pointless to follow it with a 431. Did you use a CCS for the 431?
Usually the 431 plus IC CCS makes for a simple, compact solution that is often "good enough". It can be improved upon, but not without substantial complexity, plus it is already better than 3 Terminal regulators.
Ciao T
The Salas shunt should have less dynamic impedance in the audio range and less noise. It seems pointless to follow it with a 431. Did you use a CCS for the 431?
Usually the 431 plus IC CCS makes for a simple, compact solution that is often "good enough". It can be improved upon, but not without substantial complexity, plus it is already better than 3 Terminal regulators.
Ciao T
Tazz, I'm working on Pedja's I2S splitter as well, do you use +5V supply for all (3) chips? in the datasheet the 4517 can have +5/+10/+15V, also the HC157 can take +2/+4.5/+6V. Thanks
I use 5V for easy interfacing with the rest of the logic and the dacs. You might have to select the 4517 to make sure you get one that is fast enough even then it will only work for <48K. The supply for the logic is common but with separate decoupling and beads also I only use a few gates in each package and only half the 4517 to reduce ground bounce.
I will use a cpld next time to not only split the data but also reduce the frames so its possible to feed it 192k havent decided on dither for >16bit material tough.
I will use a cpld next time to not only split the data but also reduce the frames so its possible to feed it 192k havent decided on dither for >16bit material tough.
Why not use 74F series the hc and 4517 are slow although I suppose if all 3 signals are delayed by the same amount, it doesn't really matter.
Sounds unnecessarily complicated using a shift register when you can obtain L and R datastreams with 1, 74xx02 or am I missing something?
The point is that time multiplexed I2S transfers one sample (data for L and R) in one word (WS period), at first data for Left channel, later data for Right channel. After that data of both channels converts to analog level (end of frame - WS signal).
So, if you want to have stream of data for Left channel and later in same frame inverted data for Left channel, you need to replace R data by inverted L data in this frame. Easiest way is to delay corresponding inverted L data and multiplex it onto two streams. Same for R data.
As it is done in Pedja's schematic (see attachment). It is ok for word of 64 BCK, but with small changes can be used with 32BCK word too.
If you know easier and less digitally complicated way to split I2S into such dataframes, please share with us.
Ah, now I know what your are doing.
Its not the way I would do it though.
Here is my plan for what its worth.
a) use WS to gate the data into L & R streams ( 1x 74f02)
b) Invert the msb to convert to offset binary
c) Use the dacs in simultaneous mode so no need for a shift register
d) Invert the data so you now have true and inverted offset binary data available for feeding pins 3 and 4 respectively of each dac (ie 1 dac per channel).
Bonkers suggestion for offset binary conversion....
The first bck pulse after ws goes high clocks in the msb, so feed the data to through two 74F125 tristate buffers with outputs connected, one fed with true data and one with inverted data. The inverted data buffer is only enabled for the duration of the msb bck cycle, thereafter it is disabled and the other buffer enabled, allowing the remaining 15 bits through un-inverted.
It may be necessary to delay bck and possibly ws with series connected gates to allow for the delays in processing the data.
I think it can be done with 1, 74f74, 1, 74f14 and a 74f125 but will it work? At nos speeds it should work..?
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Hi Tazzz,
IMO only NXP (Philips) HEF4517 can operate easily with +5V in such speed. Yes, it can work only <48K sampling, but if you want more, you can increase power voltage up to +15V. This theoreticaly should allow to operate <150K, 96K easily, but then will be a need to tune up input and output levels...
P.S. If someone needs HEF4517B please PM - I bought them last year from Farnell - smallest available package, still to much for me 🙂
Are you going to use upsampling to 192k, or you have digital source with such sampling rate?
For the moment I see reason only for 96k (for example output of Behringer SCR2496 after upsampling).
Or you going to split oversampled data from SAA7220?
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