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Old 13th March 2004, 12:00 PM   #21
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Default Measuring Clock Jitter

Hi JohnW,

If the clock output was fed into a monostable with say a pulse length set to 50% of the total of the clock pulse length for one complete clock cycle, then you would have a PWM output which is representative of the clock jitter. If this were filtered to remove the frequencies above say 40 to 100kHz, you could now use a sound card to measure the clock noise.

Regards

David
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Old 13th March 2004, 02:32 PM   #22
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Default Measuring Clock Jitter

Hi All,

Here is a proposed jitter detector into which a clock can be fed directly and the jitter noise will apear on the output. This can then be viewed on a PC spectrum analyser.

I will spice the circuit and get back with the results.

Click the image to open in full size.

Regards

David
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Old 13th March 2004, 03:48 PM   #23
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Quote:
Can anyone explain the differences between FM / PM in a langue I could understand – simple English would be a good start.
A PM modulation of a waveform is equal to the FM modulation of the waveform's derivative with respect to time.
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Old 13th March 2004, 05:13 PM   #24
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Default Measuring Clock Jitter

Hi All,

I have tried the circuit and although it does work the sensitivity is a bit poor for measuring clocks but does measure a signal generator FM modulated at around 11kHz as in the plot below. The modulation level is very small, probably less than 1nS as it is not visable on my scope. I know that the jitter on a TOSLINK connection is fairly obious when viewed directly on a scope screen so the circuit may be usefull for evaluating different TOSLINK cables or transmitter and receiver combinations/configurations.

Click the image to open in full size.

Regards

David
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Old 14th March 2004, 10:12 AM   #25
JohnW is offline JohnW  Hong Kong
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Hi David,

With FM / PM all the information is contained in the frequency of the carrier and not in the amplitude modulation, the frequency of the carrier can be measured by observing the zero crossings of the carrier.

The clock input (which contains the FM / PM phase noise) triggers a monostable pulse generator, which produces a short pulse at each positive (or negative) edge transition of the clock. If you then integrate the output of the monostable, you will produce an output voltage proportional to the instantaneous input frequency.

It’s very difficult to observe LF (audio frequency) jitter on a Non-Storage Scope. With LF jitter, the cycle to cycle variation can be sub pS, its only when these cycle to cycle variations are integrated over a longer time (determined by the frequency BW of interest), can the full extent of the phase noise be determined, so your 11KHz modulation levels could be quite large – but still not be visible on the scope.

This is also the same reason that the sensitivity of your circuit is so low. To increase the sensitivity, the output of the monostable needs to be integrated, rather then simply filtered. As we are trying to observe LF phenomena, the integrator must accurately “store” this LF information and not allow the LF information content of the charge pulses “leak away”.

How to provide a correctly damped (i.e. produce no spurie) “DC” stabilisation loop for the integrator?

As the total area of the pulse output from the monostable (charge) will be integrated, any amplitude modulation of the PSU (noise) of this pulse will result in an error. Logic has no PSU rejection, so an ultra low noise PSU must be used for the Monostable / comparator.

Using some of your original circuit values, the modified circuit could look something like this. U1 forms the Ultra low noise regulator to power the Logic Gates, U5, U6 form a simple High Speed comparator with a 2.5V slice point, C7, R7 form the DC stabilisation loop - they need to be calculated to provide the LPF corner fc point and achieve the correct Damping of the loop, to prevent “side-band spurie”. Ignoring the VLF voltage modulation required to stabilise the integrator's DC condition, the voltage modulation at the junction of R7 / C7 represents the LF phase noise of the clock (from DC to the LPF fc point). This is HPF by C8 / R4 to remove DC and VLF (integrator stabilisation correction voltage), and then buffered to provide the “audio” output to the FFT. U7 could also be configured to provide gain.

What do you think? is there a better method, also what FFT software do you use?
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Old 14th March 2004, 12:37 PM   #26
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Default Measuring Clock Jitter

Hi JohnW,

Great! I like the circuit but I think another integrator used to DC stabilise the signal integrator may be a better solution as the signal integrator output is then being directly monitored by the analyser and also there is very little noise injected into the circuit by the DC stabilising integrator as it is not a switching element. I noticed that your stabilising element is non inverting, has hysteresis has the integrated clock noise passing through it before it is passed on to the buffer amp. I could not see that this would give an accurate output voltage at the buffer proportional to the integral of the monostable output.

Your thoughts would be of interest.

I would like to try the new circuit as soon as possible to see what results are obtained.

HpW Works is the analyser which I mainly use plus other analysers such as SpectraLab and one from Dr Jordon (sometimes available on USA ebay for around $20 to $25).

Regards

David
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Old 14th March 2004, 02:38 PM   #27
JohnW is offline JohnW  Hong Kong
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Hi David,

I realise that I've made an error in my circuit, the DC correction loop is loaded by the HPF Resistor, pls see below for the corrected circuit.

Need To digest your sujestions and circuit more...
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Old 14th March 2004, 03:43 PM   #28
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Default Measuring Clock Jitter

Hi JohnW,

If you fed your circuit with a clock modulated with white noise and the circuit was demodulating correctly then you would have a flat line on a spectrum analyser. As the output is integrated, would you not have a sloping line with a large output at the low frequencies and a small output at the high frequencies as the integrator gain changes with frequency?

As the sensitivity is low - should it not just be a multiplier (amp with gain) on the output to raise the sensitivity of the circuit as long as the noise introduced by the amplifier is negligibly small?

Regards

David
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Old 14th March 2004, 03:48 PM   #29
JohnW is offline JohnW  Hong Kong
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Hi David,

Sorry for my last post, it appears I need to learn to spell….

The hysteresis should not be a problem; this just introduces a small DC error. Its true that U5, U6 could add noise, but would there noise contribution be any worst then the unfiltered noise of U5 in your circuit? – I really cannot comment…

Even though you take you output directly from the integrators O/P, it will still contain any noise introduced by the DC servo (OPAMP, resistor noise etc). The difference in my configuration is that it’s taken after LPF, again as to which is better, I would really not like to say, but one things for sure, if we keep throwing the suggestions and ideas back and forth – we will crack this nut eventually!

The DC accuracy of the circuit is not so import, just as long as it’s stable. The DC is removed by the output-coupling cap anyway. In the past, when I’ve tried my the configuration I’ve always found LF “Spurs” offset about the carrier on the output of the integrator. Maybe these could be removed by correct RC component values (damping) - but I’m not sure.

I’ve never used a second integrator for DC servo correction for the main integrator, so it would be interesting to see your results. My concern is that there’s no filtering on the output of the DC servo, so any servo noise is directly pumped into the main integrator – while to a limited degree, this is also true in my scheme, my method has the advantage that any noise is filtered by the LPF.

The main integrator must have very low input bias current, to preserve the LF charge information.
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Old 14th March 2004, 04:17 PM   #30
JohnW is offline JohnW  Hong Kong
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Hi David,

As I can’t simulate the circuit (my simulator - Labcenter’s Proteus is really poor with mixed signal Sims), It seems likely you will have gain drop at HF, but how much gain droop within the audio band with a 11MHz (256fs) or 16MHz (384fs) integrator output I could not say. At the end of the day, any gain drop could be compensated by a calibration plot anyway.

The problem with trying to directly amplify the output comes down to noise, the noise floor is already –130dB, the noise floor of a 5534 is about –150dBc @ 1Hz BW, so the only real way to improve the circuits performance is to directly improve its sensitivity with the integrator.

How good is your simulator? at this time I’m open to any suggestions.

Regards, John
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