Ground Bounce/ Oscillations in SPDIF

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By chance I looked at the spdif output of an Assembalge D2D twin PLL dejittered output and found quite a lot of oscillations along the top hat, at around 360 MHz on a Tek 24565 scope. The eye of the pattern is very sharp and seems to justify the low jitter claim (2 ps?) but the trest of the pattern is polluted.

I have never likedc the sound of this unit (aggressive highs) and I wonder if this is due to the oscillations. If so, what is the cure? A filter?:xeye:
 
fmak,

That is the best thing you can do for a DAC is multilayered grounds

I just finished working on the same thing but in a PS audio transport. The solution was to use a Jocko Homo clock circuit and some more stuff.

1) I pulled out the unit’s Hartley oscillator, it was connected to a 74ACT04, using all the gates, which fan out and drove the output clock and a Phillips controller. This got rid of all the ringing on the master clock for the SPDIF. Jocko and driver built in.

2) I replaced a bunch of the power supply caps with OSCON low ESR caps and added more bypass caps.

3) PS Audio used a 74ATC74 to drive the SPDIF transformer and the AESEBU circuits. They were ringing like mad. I replaced them with 74ALS74. I put them on sockets just incase I want to change them.

4) I removed the .1uf AC ground cap that connects the secondary of the transport's pulse transformer.

These changes made a world of difference in the noise transmitted to the DAC.
 
I just finished working on the same thing but in a PS audio transport. The solution was to use a Jocko Homo clock circuit and some more stuff.

I pulled out the unit’s Hartley oscillator, it was connected to a 74ACT04, using all the gates, which fan out and drove the output clock and a Phillips controller. This got rid of all the ringing on the master clock for the SPDIF. Jocko and driver built in.

These changes made a world of difference in the noise transmitted to the DAC. [/B][/QUOTE]
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Thanks, two clarifications:

You have just finished working on the Assemblage D2D, or the PS Audio transport? If it's the former, can you please email the details?
:angel:
 
FMARK,

I was working on a CD Transport and separate DAC. If your Assemblage D2D uses any of the logical families replace them. HC, HCT ACT, VHCT with ALS. Next you should check that all the logic chips are decoupled with a .1 or a .01uf ceramic cap. You should also consider changing the electrolytic caps to a OSCON versions.

I have worked on some of the older Assemblage DAC and there where quite noisy. With out having the schematics I can only make a few recommendations

http://www.jeffchan.com/audio/d2d.html
:)
 
If your Assemblage D2D uses any of the logical families replace them. HC, HCT ACT, VHCT with ALS.
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Why ALS; can you please explain?

Next you should check that all the logic chips are decoupled with a .1 or a .01uf ceramic cap. You should also consider changing the electrolytic caps to a OSCON versions.
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Have done.

I have worked on some of the older Assemblage DAC and there where quite noisy.
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I put in a 1:1 toroid transformer from the 75R output which is the only one w/o output transformer and this got rid of much of the 360MHz ringing!

The AES/EBU output which is transformer couples. doesn't seem to have a problem.



:smash:

Let me explain how I got to this, I spent some months using the D2D and was never totally happy. I currently have a Sony SCD777ES which I find to be a very good transport but there is some visible blurring (I think it's jitter) in the eye pattern of some 1.5 nS. Using the D2D , there is considerable ringing at around 360 MHz in the upper trace although the eye itself is tight.

Substituting the D2D with an older SF Ultrajitterbug, I how have improved sound both in the bass and treble, and in imaging. Blurring of the eye is reduced to 0.3 nS buried in noise.

All this was done on a TEk2465B 400MHz+ scope which seems to lock onto evereything and enables 10x zooming. Best I have got unfortunately.

It just shows that it is worthwhile looking at equipment performance.:xeye:
 
fmak

Well the Ultra Analog Receiver is a better part than the 8414 is. It is lower jitter part and has better internal isolation. Of course, it will only work to 48 KHz.

I ready do not know how the Sony interface is designed, however as stated you have loads ringing on the clock, that is bad new for the DAC.

I would start, if you have not already, so by looking at the power supplies on the DAC with the Sony SCD777ES disconnected. Not that the supplies are bad, it just easy to see what going on at the power supplies. Then Connect the Sony SCD777ES and see if the noise levels change. If the noise changes then there could be several different types of problems, circulating ground currents, ac coupling cap to ground at the SPDIF interface, and more.

Do you have schematics for the Sony SCD777ES, get one f you don't.
 
Logic Family Choice

jewilson said:
FMARK,

I was working on a CD Transport and separate DAC. If your Assemblage D2D uses any of the logical families replace them. HC, HCT ACT, VHCT with ALS.

:)

Hi Jim,
Traditionally HC logic is used for digital audio. I once tried VHC logic and found it better sounding than HC or AC logic.
I have no experience with ALS but I can of course give it a try.
The more it experiment the more I am convinced good digital sound stands or falls with the clock in the transport.
:bigeyes:
 
Elso,

When your switching at high clock speeds, High Speed CMOS dumps more current to ground the Advanced Low Power Schottky.

I was looking for my older data books that show the differences output designs between the two, however I could not find the applications and schematic data for the High Speed CMOS. I have the stuff for ALS in some of my old TI data books. If I find the more I will post it. :)

Also, as the clock speed increases for High Speed CMOS the it will use more power than ALS at high speeds.
 
Logic

jewilson said:
Elso,

When your switching at high clock speeds, High Speed CMOS dumps more currect to ground the Advanced Low Power Schottky.

I was looking for my older data books that show the differences output designs between the two, however I could not find the application and schematic data on the High Speed CMOS. I have the stuff for ALS in some of my old TI data books. If I find the more I will post it. :)

Jim,
Please read the more I experiment the more etc. in my post.
Seems like someone changed position of the keys on my keyboard. Is this some new kind of virus?:clown:
ALS is bipolar logic. HC and VHC is CMOS logic I learn from Fairchilds logic selection guide.:cool:
 
Re: Logic Family Choice

Elso Kwak said:


Hi Jim,
Traditionally HC logic is used for digital audio. I once tried VHC logic and found it better sounding than HC or AC logic.
I have no experience with ALS but I can of course give it a try.
The more it experiment the more I am convinced good digital sound stands or falls with the clock in the transport.
:bigeyes:

You mean clock next to DAC chips, wherever they may
be.

T
 
jewilson said:
Elso,

When your switching at high clock speeds, High Speed CMOS dumps more current to ground the Advanced Low Power Schottky.

I was looking for my older data books that show the differences output designs between the two, however I could not find the applications and schematic data for the High Speed CMOS. I have the stuff for ALS in some of my old TI data books. If I find the more I will post it. :)

Also, as the clock speed increases for High Speed CMOS the it will use more power than ALS at high speeds.

There was a post with comparison of jitter figures of different
logic types some time ago. ALS was worse than most other types,
HOWEVER, gnd noise is real issue. XO should reclock at DAC
chips and remove (attenuate) that jitter.

Might be an advantage in changing the reclocking DFF logic family
only to something of lower jitter and sacrifice small increase in
gnd noise for that 1 application.


T
 
Jitter of Logic Families

Terry Demol said:


There was a post with comparison of jitter figures of different
logic types some time ago. ALS was worse than most other types,
HOWEVER, gnd noise is real issue. XO should reclock at DAC
chips and remove (attenuate) that jitter.

Might be an advantage in changing the reclocking DFF logic family
only to something of lower jitter and sacrifice small increase in
gnd noise for that 1 application.


T

Hi Terry,
I have seen that post by a Russian(?) forum member. I wondered if actually jitter was measured instead of propagation delay as the fastest logic apparently had the lowest jitter.
As I am using a NON-OS DAC with I2S Direct. I don't use the masterclock at the DAC and have it in the transport as close as possible to the DSP.
I don't use the Asynchronous Reclocker any more, as I don't see any reason using it with I2S Direct, but it seems I have created another "monster". They will never let it die, or me rest."
:(
 
Re: Jitter of Logic Families

Elso Kwak said:


Hi Terry,
I have seen that post by a Russian(?) forum member. I wondered if actually jitter was measured instead of propagation delay as the fastest logic apparently had the lowest jitter.

:(

Hi Elso, I don't think so as prop. delay is usually in nanosecs
for non - ecl logic families. It seems consistent that the
faster logic has lower jitter but more ground induced noise
however I am no expert in this area.



As I am using a NON-OS DAC with I2S Direct. I don't use the masterclock at the DAC and have it in the transport as close as possible to the DSP.
I don't use the Asynchronous Reclocker any more, as I don't see any reason using it with I2S Direct, but it seems I have created another "monster". They will never let it die, or me rest."
:(

Maybe you should reclock I2S with a DFF/line driver right at
transport OP. This will ensure lowest jitter.

What cabling are you using for I2S to dac? Are you using 75ohm
transmission line and separate coax's?

Terry
 
Re: Re: Jitter of Logic Families

Terry Demol said:


Hi Elso, I don't think so as prop. delay is usually in nanosecs
for non - ecl logic families. It seems consistent that the
faster logic has lower jitter but more ground induced noise
however I am no expert in this area.



Maybe you should reclock I2S with a DFF/line driver right at
transport OP. This will ensure lowest jitter.

What cabling are you using for I2S to dac? Are you using 75ohm
transmission line and separate coax's?

Terry

Hi Terry,
Then we should ECL which is the fastest and has the lowest jitter, and does not have groundbounce as Jocko once explained???:confused:
I have tried reclocking I2S with I2S Direct that is transporting the three signals Wordclock, Bitclock and Data to the DAC and reclocking these in the DAC asynchronously. It was not worth the extra trouble and did not give an improvement. In fact sonically it is slightly worse.
I am using 50 Ohm coax cables as in my original post.
http://www.diyaudio.com/forums/showthread.php?postid=249220#post249220
Of course 75 Ohm cables could be used as well.
:cool:
 
Terry,

Having the fastest chip in your circuit does not guarantee you good jitter performance.

If the master clock as jitter then you have jitter.
If the layout is poor with distributed capacitance and inductance, that will effect the jitter.
If the transformer has poor coupling then you can have poor jitter.
If your circuit has poor grounding and is noisy, you are going to have jitter.
If you have impedance mismatches and reflections well you know.
If you have slow rise time on you clock edge that can cause jitter.

Low jitter performance comes down to a design that implements all these elements to make a system with low jitter. It a recipe in hardware design too.
 
diyAudio Retiree
Joined 2002
Half fast

The faster the edge rates in this interface, the more RFI, reflections, and noise. RF noise can more easily couple through the interwinding capacitance when using a pulse transformer for the interface. Stick to HC CMOS. I once did some measurements and poked around inside a very expensive top loading transport. It had 4000 series CMOS, which is even slower, driving the output, and still sounded extremely good.
 
jewilson said:
Terry,

Having the fastest chip in your circuit does not guarantee you good jitter performance.

If the master clock as jitter then you have jitter.
If the layout is poor with distributed capacitance and inductance, that will effect the jitter.
If the transformer has poor coupling then you can have poor jitter.
If your circuit has poor grounding and is noisy, you are going to have jitter.
If you have impedance mismatches and reflections well you know.
If you have slow rise time on you clock edge that can cause jitter.

Low jitter performance comes down to a design that implements all these elements to make a system with low jitter. It a recipe in hardware design too.

Hi Jewilson,

You are probably new here and don't realise but, all these topics
have been covered in depth and pretty much go without saying
(in my world).

The issues were that ALS/AS has low noise / gnd bounce but
has more jitter per gate than most other logic families.
So better to use slower lower noise logic everywhere possible
but reclock at DAC chips directly from XO. I was suggesting that
maybe *only the 1 DFF that does reclocking at DAC* would
benefit from faster lower jitter logic at the sacrifice of *some*
small increase in noise for that 1 part.

Cheers,

Terry
 
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