Ground Bounce/ Oscillations in SPDIF

[Terry Demol]

Originally posted by jewilson
Elso,

When your switching at high clock speeds, High Speed CMOS dumps more current to ground the Advanced Low Power Schottky.

I was looking for my older data books that show the differences output designs between the two, however I could not find the applications and schematic data for the High Speed CMOS. I have the stuff for ALS in some of my old TI data books. If I find the more I will post it.

Also, as the clock speed increases for High Speed CMOS the it will use more power than ALS at high speeds.

There was a post with comparison of jitter figures of different
logic types some time ago. ALS was worse than most other types,
HOWEVER, gnd noise is real issue. XO should reclock at DAC
chips and remove (attenuate) that jitter.

Might be an advantage in changing the reclocking DFF logic family
only to something of lower jitter and sacrifice small increase in
gnd noise for that 1 application.


T

[jewilson]

Terry Demol,

So why don't you find us that information regrading logic chips and ground noise.

[Terry Demol]

Originally posted by jewilson
Terry Demol,

So why don't you find us that information regrading logic chips and ground noise.

Well, you could ask nicely instead of demanding
and I might think about it

BTW it was jitter comparisons not gnd noise.

T

[Elso Kwak]

Originally posted by Terry Demol


There was a post with comparison of jitter figures of different
logic types some time ago. ALS was worse than most other types,
HOWEVER, gnd noise is real issue. XO should reclock at DAC
chips and remove (attenuate) that jitter.

Might be an advantage in changing the reclocking DFF logic family
only to something of lower jitter and sacrifice small increase in
gnd noise for that 1 application.


T

Hi Terry,
I have seen that post by a Russian(?) forum member. I wondered if actually jitter was measured instead of propagation delay as the fastest logic apparently had the lowest jitter.
As I am using a NON-OS DAC with I2S Direct. I don't use the masterclock at the DAC and have it in the transport as close as possible to the DSP.
I don't use the Asynchronous Reclocker any more, as I don't see any reason using it with I2S Direct, but it seems I have created another "monster". They will never let it die, or me rest."

[Terry Demol]

Originally posted by Elso Kwak


Hi Terry,
I have seen that post by a Russian(?) forum member. I wondered if actually jitter was measured instead of propagation delay as the fastest logic apparently had the lowest jitter.

Hi Elso, I don't think so as prop. delay is usually in nanosecs
for non - ecl logic families. It seems consistent that the
faster logic has lower jitter but more ground induced noise
however I am no expert in this area.

As I am using a NON-OS DAC with I2S Direct. I don't use the masterclock at the DAC and have it in the transport as close as possible to the DSP.
I don't use the Asynchronous Reclocker any more, as I don't see any reason using it with I2S Direct, but it seems I have created another "monster". They will never let it die, or me rest."

Maybe you should reclock I2S with a DFF/line driver right at
transport OP. This will ensure lowest jitter.

What cabling are you using for I2S to dac? Are you using 75ohm
transmission line and separate coax's?

Terry

[Elso Kwak]

Originally posted by Terry Demol


Hi Elso, I don't think so as prop. delay is usually in nanosecs
for non - ecl logic families. It seems consistent that the
faster logic has lower jitter but more ground induced noise
however I am no expert in this area.



Maybe you should reclock I2S with a DFF/line driver right at
transport OP. This will ensure lowest jitter.

What cabling are you using for I2S to dac? Are you using 75ohm
transmission line and separate coax's?

Terry

Hi Terry,
Then we should ECL which is the fastest and has the lowest jitter, and does not have groundbounce as Jocko once explained???
I have tried reclocking I2S with I2S Direct that is transporting the three signals Wordclock, Bitclock and Data to the DAC and reclocking these in the DAC asynchronously. It was not worth the extra trouble and did not give an improvement. In fact sonically it is slightly worse.
I am using 50 Ohm coax cables as in my original post.
http://www.diyaudio.com/forums/showt...220#post249220
Of course 75 Ohm cables could be used as well.

[jewilson]

Terry,

Having the fastest chip in your circuit does not guarantee you good jitter performance.

If the master clock as jitter then you have jitter.
If the layout is poor with distributed capacitance and inductance, that will effect the jitter.
If the transformer has poor coupling then you can have poor jitter.
If your circuit has poor grounding and is noisy, you are going to have jitter.
If you have impedance mismatches and reflections well you know.
If you have slow rise time on you clock edge that can cause jitter.

Low jitter performance comes down to a design that implements all these elements to make a system with low jitter. It a recipe in hardware design too.

[Fred Dieckmann]

The faster the edge rates in this interface, the more RFI, reflections, and noise. RF noise can more easily couple through the interwinding capacitance when using a pulse transformer for the interface. Stick to HC CMOS. I once did some measurements and poked around inside a very expensive top loading transport. It had 4000 series CMOS, which is even slower, driving the output, and still sounded extremely good.

[jewilson]

Fred,

Sound like implementation counts. Man 4000 series CMOS try running that at 5 volts, talking about slow.

[Terry Demol]

Originally posted by jewilson
Terry,

Having the fastest chip in your circuit does not guarantee you good jitter performance.

If the master clock as jitter then you have jitter.
If the layout is poor with distributed capacitance and inductance, that will effect the jitter.
If the transformer has poor coupling then you can have poor jitter.
If your circuit has poor grounding and is noisy, you are going to have jitter.
If you have impedance mismatches and reflections well you know.
If you have slow rise time on you clock edge that can cause jitter.

Low jitter performance comes down to a design that implements all these elements to make a system with low jitter. It a recipe in hardware design too.

Hi Jewilson,

You are probably new here and don't realise but, all these topics
have been covered in depth and pretty much go without saying
(in my world).

The issues were that ALS/AS has low noise / gnd bounce but
has more jitter per gate than most other logic families.
So better to use slower lower noise logic everywhere possible
but reclock at DAC chips directly from XO. I was suggesting that
maybe *only the 1 DFF that does reclocking at DAC* would
benefit from faster lower jitter logic at the sacrifice of *some*
small increase in noise for that 1 part.

Cheers,

Terry