Asynchronous Sample Rate Conversion

[CraigBuckingham]

Originally posted by Guido Tent



on chip crosstalk

On a PCM63 it was that bad, that reclaocking wclk and data helped. On smaller packages it is different, no experience (yet)

best

Hi Guido,

For the PCM63 did you evaluate the re-clocking for each input separately and then both together?

Best regards, Craig.

[Kurt von Kubik]

This thread is simply amazing, and my post here shall only be for the purpose of bringing it up on the frontpage once again to remind about the brilliant work of Wherewolf.

[Guido Tent]

Originally Posted by CraigBuckingham

Hi Guido,

For the PCM63 did you evaluate the re-clocking for each input separately and then both together?

Best regards, Craig.

hello Craig,

It is about 12 years ago. We made a circuit that indeed enabled us to evaluate reclocking on data, wclk and le separately.

The Latch was most sensitive to reclocking, as expected. Data and wclk where slightly sensitive, reclcoking improved playback quality but only about 10% of the improvement made when reclocking LE.

Needless to say that one needs separate reclockers AND power supplies for all 3 signals, as we implemented in all our newest DAC designs.

best