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#1 |
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diyAudio Member
Join Date: Sep 2002
Location: Malaysia
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hi
i built the cdpro2 and also the tda1545 dac. but can't use them as the cdpro2 outputs i2s and not eiaj. any idea how to make the cdpro2 output eiaj? it seems i need to do something to the dsa software. but i have no idea how. can i do it hardware wise? please advise. thanks. donjuan |
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#2 |
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diyAudio Member
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I've done this with vae1250 mechanism, i guess the command set is the same. I should search for the modified eprom, but as VAE1250 is discontinued I don't have them anymore to test.
Anyway you need an eprom programmer to burn the soft... |
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#3 |
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diyAudio Moderator Emeritus
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The cdpro2 unit does support EIAJ, and a simple command needs to be issued over the DSA interface. I don't know you have your control board setup, but here is the command that needs to be issued.
-- Brian |
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#4 |
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diyAudio Member
Join Date: Nov 2002
Location: Grenoble, FR
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Brian, when you use the 2FS or 4FS mode, is it oversampled or upsampled?
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#5 |
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diyAudio Member
Join Date: Sep 2002
Location: Malaysia
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hi guys
thanks for all the reply. any other way other than dsa communication using a pc? i was hoping for hardware changes but looks like fat chance... donjuan |
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#6 |
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diyAudio Member
Join Date: Oct 2001
Location: .
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Why hardware not software?
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#7 | ||
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diyAudio Moderator Emeritus
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Quote:
Quote:
I will organize a group order sometime in the future for the controller that I designed. Gallery from my project at: http://brian.darg.net/cdpro2 -- Brian |
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#8 |
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diyAudio Member
Join Date: Sep 2002
Location: Malaysia
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why hardware but not software?
well, if it's hardware, it's easier for me to incorporate. i can't access the firmware inside. hi brian interested in your controller! donjuan |
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#9 |
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diyAudio Member
Join Date: Sep 2003
Location: Singapore
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I have done a EIAJ to I2S converter by delaying the LRCLK EIAJ signal by 7 BCK clock cycles by means of a shift register. You can see the schematic and PCB in my post on sharing my digital work.
I have not tried it but I see no reason why the scheme cannot work by delaying data by 7 clock cycles instead of delaying LRCLK as a means of converting from I2S to EIAJ. |
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