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Prune 9th February 2004 01:41 PM

CS43122 output
 
In the CS43122 datasheet it says the differential mode output is 1.33VREF, with commond mode 0.5VREF. How is that possible if VREF is equal to the analog power supply voltage VA (5.5V) and there's no negative supply? 1.33 * 5.5V = 7.315V and that's a range beyond the power supply voltage range!
What am I missing here? :scratch:

Norman Tracy 9th February 2004 08:42 PM

Re: CS43122 output
 
Good question.

You are missing the meaning of "common mode 0.5VREF"

VREF is typically 5.5 volts so 0.5VREF = 2.75

now

1.33 * 2.75V = 3.6575V which is below the five volt analog supply.

The part that may not be clear is all these new DACs from Crystal, BB/TI, & AKM which run off +5 (or 3.3V) uni-polar supplies bias their outputs which is where the 0.5VREF comes in. In the case of CS43122 when its outputting silence (aka digital zero) the outputs sit at 0.5VREF = 2.75 volts.

As it outputs a positive going signal the differential pairs, lets use the left channel AOUTL- (pin 24) and AOUTL+ (pin 23) as examples, move differentially towards the V rail and ground respectively. The 1.33 factor relieves the chip of needing to go all the way to it's rail or ground. Therefore when reproducing a full scale signal AOUTL+ = 3.6575V and AOUTL- = 3.6575 - 2.75 = 0.9075V. Say itís a sine wave being reconstructed then the next half cycle when its at maximum negative AOUTL+ = 0.9075V and AOUTL- = 3.6575V.

It is the job of the following analog stage to take the differential voltage outputs combining them while its CMRR ignores the DC offset yielding the more typical signal with its zero point referenced about 0 volts.

Spartacus 9th February 2004 09:00 PM

Hi Norman,

are your CS43122 boards done yet? How is the DAC sounding?

Prune 10th February 2004 12:14 AM

I was asking because I'm trying to figure out something about jwb's CS43122 DAC. The output stage is a follower which, on my implementation, gives about -0.8V DC offset, whereas the DAC chip can output 0.9V amplitude. As I'm a newbie to electronics I'm sorry for asking a stupid question, but is there any problem if the output waveform crosses 0V? Running this in LTSpice doesn't show a problem but I want to make sure. And if it's fine, is it possible to adjust the DC offset to 0 so I won't need DC blocking output capacitors (it's hard to fit large value quality film capacitors in the enclosure, and smaller ones attenuate lower frequencies in low impedance loads too much).
Thanks for answers :)

jwb 10th February 2004 04:58 AM

My "cheap" DAC series isn't designed for DC coupling. The outputs really need to be AC coupled. Yes, the follower adds a -Vgs offset to the signal, which puts it below ground at steady state. As I mentioned before you are certainly welcome to try driving the line right off the 43122, but I don't think it has the oomph to do it.

As for the blocking caps, use a good quality film cap and you won't notice. Try something in the neighborhood of 8uF polypropylene.

And there's no problem if the output crosses 0V. To understand why, you need to separate the DC and AC domains in your mind. The AC signal doesn't care what the DC bias point is.

Prune 10th February 2004 05:37 PM

Thanks. It's just that with capacitors, if I simulate driving a low impedance load, especially differential, the 20Hz end falls down by several dB unless I use very large ones, and 10uF films are the most I can fit in.

jwb 10th February 2004 05:43 PM

Don't drive a low-impedance load.

Prune 10th February 2004 06:50 PM

LOL!

What about putting the capacitors to the gates of the IRFs instead and using voltage dividers to bias them? Using a pot would allow adjustment of the output DC then, and the thing could drive loads under 1K then.
Or what about using a zener or LED voltage shifting?


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