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Old 10th October 2002, 06:01 PM   #21
tiroth is offline tiroth  United States
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Generally in the case of multiple ground pins they are connected in the substrate. In this case connecting the pins to different grounds (=> different inductances with respect to power supply ground) will result in circulating ground currents within the substrate. Not good.

The manufacturer is probably the best source for information about the topology of an IC.
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Old 11th October 2002, 10:42 AM   #22
guido is offline guido  Netherlands
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Kenev,

Working on double sided PCB with 2 TDA1541's aswell.
If you have space for one '74 flipflop, one 4517 shift
register and one 20V8 GAL, the TDA's will be split into
left and right (one for left, the other for right channel -
output differential as choice).

I am now working on a clock in the DAC and feeding it back to
the player (FIFO register to avoid sync problems).
All on one Eurocard sized board (but not the clock, powersupply
or analogue output).

So i also have to figure out how to do the grounding.
What i did now:

AGND and DGND of the TDA connected under the DAC.
The name of the pin says to what they are connected on the inside,
not what they should be connected to on the outside. From an old
analogue devices application note (dont know if it is the one
from the start of this post, link doesn't work. Have a papercopy)
i could find that AGND and DGND should be connected to the analogue
groundplane. The PCM63 datasheets also says that explicitly (Elektor
did not read this when they made their first DAC...).

filtercaps and analogue powersupply (was it the -15V,
cant remember right now) connected to AGND pin.

GND of the digital logic connected to DGND on the board.
DGND powersupplies connected to the DGND pin.

I plan to use separate transformers (trannie's, my english fails here) for
each powersupply to avoid having the grounds connected at the powersupplie aswell.

I have decoupling with one small cap at all digital logic ic's and an oscon with two smd caps
(like thorstens DAC) on the TDA powersupply and the clock divider IC).
No resistors in the signal lines and no ferrite beads now, should i change this ??

There are two separate groundplanes on the board on the toplayer, currently connected to nothing.
I don't know where to connect them to gnd yet, maybe at the powersupply connectors ?

All of this results, i think in a short returnpath for the data,ws and clock signal from the digital
part back to the logic. Also short returnpath for the analogue signals to AGND, without going over the
digital GND lines (output, supply and filtercaps also have different tracks back to AGND pins).
Then one track between DGND and AGND per DAC.

The DAC GND are connected together on the border of the analogue (DAC) and digital part, close to the
digital logic (so they don't share much track there). Now my problem (?) I create a huge GND loop
on the analogue side of things. From this common gnd point to the DGND pin to the AGND pin of a DAC, then
to the output post to the output stage, from there or even in the preamp back to the output post of
the other DAC, to AGND, DGND and then back to the common point. Bad idea ???
I was figuring there should not much currents going between the analogue and digital GND pins of the DAC
and between them. But maybe i am totally wrong !!! Or can i get away with it, by using audio transformers
in the output stage.

Sorry for the long post, hope for some reply from the experts (i'm not, i am called Guido and also from Holland.
But i am not Guido Tent :->).

To give you some idea's, i posted the first version of the PCB design. Schematics will follow if it all
works..

Greetings,

Guido

PS, made a PCB for a DSP + ADC way back in school. It worked, but the DSP quit the with the ADC port
(serial port to ADC) now and then. We bought a second DSP before we figured out the GND plane was crap.
It was fixed with a wire from ADC GND to DSP GND (creating a nice loop...). But then it never quit.
Bad PCB design.
Attached Files
File Type: zip dac.zip (62.8 KB, 114 views)
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Old 11th October 2002, 10:58 AM   #23
guido is offline guido  Netherlands
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Some comments after re-reading..

-statement on PCM63 DAC gnd was only as example.
-elektor split agnd and dgnd with resistor between agnd and dgnd pin on their PCM63 DAC..
-is a trannie a transformer? Again, my enligh fails
-when you look at the top layer (with the gnd planes), the two tracks crossing the separation on the board are the gnd tracks from DACs back to logic. Also you can see the smd caps on the dgnd pins and the track to the DGND pin of the dac. The IC in the top of the digital part is the clock divider, there the GND from the DAC's are connected to the logic part. Just under it, the GND's of the DAC's are connected.
-On the bottom side, the connection between DGND and AGND is the track under the DAC. On the AGND some kind of "star" towards the output, supply and filter caps.
-I still have to ajust pad sizes etc.

Guido
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Old 11th October 2002, 11:57 AM   #24
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dear all,

I am happy to note all interest on layout and ground planes and related suff.

Wrt multple ground pins: They should see as much as possible (!) the same potential, as internal circuits relate to these, and signals go from analog to digital domain at least once (internally that is).

Decoupling caps, being supply, filter or internal reference, should ofcourse be connected to the right ground (or reference) pin. Very often a star like strucure from that pin to relevant decoupling caps is proposed, to avoid voltage buildup across the plane.

Ofcourse all ground pins are connected to the same plane.

While RF emissions are not our (DIY) highest concern, my experience is that pushing them down, sound quality increases.

I wrote an article a while ago, on layout and stuff. It can be found here:

http://members.chello.nl/~m.heijlige...decoupling.pdf

enjoy

Guido Tent
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Old 11th October 2002, 12:57 PM   #25
tiroth is offline tiroth  United States
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Guido, just a warning, that board looks like slot antennae nightmare! Digital lines should be everywhere above (below) a solid ground plane. The return is going to mirror the digital line on the plane. In addition to high radiated EMI, there are going to be large circulating ground currents because there is not a low-inductance return from AGND. One solution would be a bridge across the moat, and route all traces under it. This would require rethinking your analog grounding scheme though. (It is a little hard to tell exactly what is going on with your board w/o any descriptors though) Even then, your top-ground plane looks like it has slot antenna potential with those traces cutting through it, but I do not have the expertise to address that. Jocko designed what looks to be a nice board with top-ground for the analog section, so maybe take a look at that and talk to him. I don't think he routed anything significant on the ground layer.

I would recommend taking a look at some of the articles I've referenced previously. In particular, completely splitting the plane tends to be not recommended.

At the risk of giving advice above my level of comprehension, I'm going to say that I think either balanced output or output xform are going be mandatory. Otherwise you have either circulating ground currents or the giant loop you describe. I think unless your interconnects are short, very low resistance, and very low inductance, the quality might not be what you are aiming for.

Also, two other notes. I think series resistors on the signal lines are a great idea: they only slow the edge a little bit but provide some nice impedance to circulating currents. And, I would consider paying a lot of attention to the decoupling of all the ICs. When your "unimportant" 7400 IC switches garbage into the supply lines it is going to get into your "important" digital ICs, etc.
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Old 11th October 2002, 01:26 PM   #26
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dear Tiroth

Thank you for your mail, your remarks are correct, however, If you take a peek at the rest of the site

http://members.chello.nl/~m.heijlige...tml/dactop.htm

you will not that:

- we use a 4 layer board with all signal lines inbetween 2 ground layers (the 4th layer is used for "LF" lines like power and status signals)

- The ground planes are NOT interrupted at all

- We extensively decouple ALL IC's with a capacitor and series inductor (like I reccomend in my article)

- The RF excitation of I/O (like analog output) is mainly caused by the voltage build-up across the board. By design we kept that low

Going balanced may be a sollution, but due to the parasitic behaviour (lack of CM reduction) it won't help above say 30 MHz.

best regards

Guido Tent
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Old 11th October 2002, 01:44 PM   #27
tiroth is offline tiroth  United States
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Guido Tent,

Sorry for the confusion! My reply was to (just) Guido, not yourself. I've read your article in the past and gotten some inspiration from it. :)

My comment about going balanced was only to prevent ground currents. (no need to connect ground!) Dr. Johnson commented once on Sigcon that maintaining a single connection from AGND to DGND was key, else digital currents almost invariably contaminate the analog plane, regardless of other measures taken.

Tyler
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Old 11th October 2002, 03:46 PM   #28
guido is offline guido  Netherlands
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Hi,

Sorry for the confusion, i'll call myself Guido B. from now on... ;-)
Tyler, thanks for the reaction. I need feedback, so im am trying to understand your comments:

"Digital lines should be everywhere above (below) a solid ground plane" - Ok, this is a problem for me with the
digital logic. I only have 2 layers and i cannot use via's. Which i could have a 4 layer board.. :->
I need the two layers on the logic side to get the stuff routed. Guess i need more integrated logic..

I was not using the groundplane as return (the GND tracks are separate from the GND plane in the digital part).
I can do a redesign of the digital part and use the top layer as ground and the other layers for the other tracks.
See if i manage.

"there are going to be large circulating ground currents because there is not a low-inductance return from AGND"
Sorry, i cannot follow this. Moat: my english dictionary says it is the water around a castle. :->
Could you explain a bit more ?

The tracks through the analogue groundplane are returning GND from the logic part towards the DGND pin
(first passing the decoupling caps of the DAC, the SMD stuff you see on the top side).
I could make this plane also just a solid one.

"completely splitting the plane tends to be not recommended" I thought to have the two GND planes only as shielding.
The tracks on the top side ARE the GND tracks between analogue and digital connecting the analogue and digital parts
as short as possible (groundwise).

The "giant loop" is indeed the concern i have. Now i have more :->
After the DACs i need to make the outputstage (I/V conversion). There i can connect GNDs together again.

Series resistors in the data and ws line, ok sounds good. 500 Ohms i thought is a good value (?)
But i don't want to slow the edge on the clockline to the DAC, so i guess not in there.

Decoupling, yes all the logic chips have a cap (next to the gnd pin, as described by Guido Tent).
The clock divider has an oscon and two smd caps (like thorsten's adagio). The divider 74AC161 IC i think
is one of the "important" ICs: it divides the clock before it goes to the DACs :-)

So what to do
- Solid plane above the digital logic, used as gnd there?
- Solid plane above the analogue part, used as gnd there (solves my loopproblem)?
- if both=yes, connect the gnd planes in the middle of the board with a track following the clockline track from
the digital part to the analogue part (on the opposite side of the board offcause)?
- make one huge groundplane on the top for all GND and connect all to it.

Thank you for you reactions, i need them!

Guido, wellicht neem ik contact op om weer zo'n klokkie te kopen (11.8MHz).

Greetings,

Guido B.
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Old 11th October 2002, 04:56 PM   #29
tiroth is offline tiroth  United States
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Guido B, ^_^

The ground plane in a digital circuit reduces EMI, but not just by shielding. It creates a low-inductance ground path, so your ground returns don't have to act like antennae. Having individual ground traces in a digital circuit is close to worst-case: these traces will have high inductance and cause a great deal of ground bounce. (and EMI, etc)

Remember, high speed digital currents follow the path of least inductance. You can't control them so easily as low-speed analog currents. If you don't present a low-impedance ground, they will travel on your supply lines instead.

You can make your own vias with PCB pins or bits of wire. As for "moat", your english is indeed correct, although this is an unusual usage. See my link above. You won't need the "multiple moats" but a single one will suffice. Recommended reading is "High Speed Digital Design" by the same Dr. Johnson.

P.S. Jocko managed to convince me to stay away from AC logic. Unless you need fast logic, definitely stick with HC, after that consider F(AST). You are doubling the amount of care needed when you move to AC from HC.
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Old 12th October 2002, 09:52 AM   #30
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dear all,

Good discussion going on, happy to note you guys take this subject serious (manufacturers could take note of this)

Let me take this opportunity to elaborate a little on loops, EMI, and groundbounce. Most results I list are measured results, from the time that I worked at Philips Semiconductors.

Currents run in loops (think currents, voltages are just the result of these and impedances).

A loop as such radiates. The amount depends on the loop area, frequency and current amplitude.

Consider a round loop. Connect a 2 wires, with their nodes at 3 o'clock and 9. Once a current runs through the loop, a voltage appears in-between the wires (due to the loop impedance)

This voltages excites both wires: We now have a di-pole antenna which radiates. The voltage source can be present in your groundplane, as currents run through the plane.

Consider an average PCB, with wires attached (and refered to ground, at least for RF) at left and right side. in the middle is your RF/digital chip, generating currents through the plane: there you are !

So 2 mechanisms cause radiation:

- Loops
- Voltages exciting wires

It depends on the size of the PCB, but at an average 10 cm, the loops start dominating at 500 MHz: Below the attached wires dominate. Above holds for antenna measurements at 3 meters distance.

Now back to the PCB design. Following above, you want to

- reduce loop size
- reduce the voltage build up across the plane (also for signal integrity (read: jitter)

Loop size reduction is obvious, as long as you asure that the current IS ABLE to run in the smallest loop possible. Design the PCB accordingly and make sure you know where currents run.

Besides reducing loop size, reduce the current and the bandwidth to the minmum required!

Voltage buildup can be reduced by preventing currents to run through the plane. A simple example is to (physically) locate the decoupling cap as close as possible to the ground pin of your IC ground pin. As such, the smallest piece of ground plane is incorporated.

On the subject of splitting grounplanes: I see reccommendations on only connecting the planes underneath the A/D or D/A part of the circuit. This connection closes the loop of the internally generated currents that cross the A to D border.

This may be allowed, but only if you are very sure that no other currents need to cross that same border !

all the best

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