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Old 5th March 2002, 04:31 PM   #1
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Talking AD1854 pitfalls and first listening results

Last night, I got my AD1854 to work finally. I had already desoldered my first chip thinking I had fried it with ESD, but I simply didn't read the data sheet well enough (the information can be hidden).

The first problem was that I had set X2MCLK to high, assuming that this was the correct setting for a 16.9344 MHz clock. The description reads: "Selects internal clock doubler (LO) or internal clock = MCLK (HI)." However, in table II the correct setting is given. Apparently, the AD1854 needs an internal clock of at least 512x f_s at single speed operation. I wonder whether this clock doubling action is good for jitter, but then, all the specs are given with at 256x rather then the probably more favorable 512x internal clock

The second problem was the reset/power down pin. The description reads: "The AD1854 is placed in a low power consumption mode when this pin is held LO. The AD1854 is reset on the rising edge of this signal. ... Connect HI for normal operation."

There is no mention anywhere that it actually needs an external reset. So I used a 4.7 k pull-up. The outputs would hang at 0.3 and 4.5 V. When I shorted the pin to ground for a moment, they would settle at 2.4 Vs each which is ok. Connecting a 470 nF capacitor to ground did not help, apparently, the rise is too slow. Small wonder the AD1853 evaluation board uses a reset generator chip. I think it could also be built from an LM311 comperator. Or one could simply steal the reset pulse from the CD player...


OK, what was the configuration? Serial data were simply stolen from the decoder chip and sent through a ribbon cable (anybody know the characteristic impedance of 1/20 inch computer ribbon cable with every second wire used as ground?), with 270 R series resistors in front of the DAC. The clock signal was also stolen from the CD-player. Except for beefing up the decoupling of the oscillator gate, nothing was changed, even the mediocre ceramic resonator stayed in place. Pk-pk period jitter was 350 ps (oscilloscope jitter arount 70 os pk-pk). This is not good but by no means completely unadequate. I will inject my ECL clock (which is also on my board, but still disabled) later.

I had a seperate supply with lots of passive filtering and LM337 and LT1086 for regulation. The op-amp supply has no on-board regulation, but I have SMD 7805 regulators for both analog and digital supplies of the AD1854. The output filter followed the topology suggested by AD with a 40 kHz cutoff frequency. I used hand-matched 1% 1/4 W metal film leaded resistors and WIMA stacked polypropylene capacitors. I am not convinced that this topology which combines differential-to-single-ended conversion and second order low-pass filtering in a single op-amp is optimal, but that is for later boards... The op-amp was an OPA2604 that I had sitting in the shoebox. Nothing spectacular, all in all, but with superior supply decoupling and good passive components.

What does it sound like? Surprisingly good, considering that the clock was still poor and that both op-amp and DAC are not top-of-the-line products. I could not do any A/B-tests as both my modified Philips CD-931 (bitstream SAA7350) and Sony CDP-M 25 (4x oversampling, Sanyo 16 bit ladder DAC) had died shortly before. But I am beginning to think that intensive listening to a couple of well-recorded CDs may be more meaningful anyway.

The sound was very unpretentious and at the same time very warm. The sound-stage was very broad and gave sufficient localization that appeared very harmonic. The sound did not have that attractive perkyness of the Sony that jumped at you and gave a very precise localization of acoustic guitars. On the other hand, voices and instruments sounded much more natural on the AD1854. I am not sure whether the Sony added some distortion that gave it this directness or whether it was due to it superior clock and shorter digital filter.

In comparison to the Philips, the whole performance was definitely more musical and not as analytical. In comparison to the analog out (unmodded except for supply bypassing) of the Kenwood player I am now abusing as a transport, the difference was mind-boggling. Gone all the coldness. The soundstage no longer retreated far behind the speakers....


Will keep you posted on experiences once the clock source is changed.
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Old 5th March 2002, 10:11 PM   #2
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Hi Eric,

Nice to have some listening impressions in this rather dry forum Sounds great (pun time...)

How did you solve this reset problem ? (I may have read it wrong...)

Just my two cents now :

Quote:
Serial data were simply stolen from the decoder chip and sent through a ribbon cable (anybody know the characteristic impedance of 1/20 inch computer ribbon cable with every second wire used as ground?), with 270 R series resistors in front of the DAC.
Well, I'm not sure I understand you right, but the Zc of such a cable typically ranges from 95 to 105 Ohms (manufacturer dependant) when used in the following configuration :

-------------------- Gnd
==================== Signal
-------------------- Gnd
-------------------- Gnd
==================== Signal
-------------------- Gnd
etc.......

So I think it would be better to lower your 270 R series resistors down to 50-100 R, and to locate it at the outputs of the decoder/filter rather than near the DAC input.

Tell us what you get with you ECL clock.

Cheers,
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Old 5th March 2002, 11:42 PM   #3
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Default AD1854

I love it when you talk signal integrity François! I concure on source termination (50 ohm) and cable Z. Good termination, grounding, and decoupling will yield audible results. For some good material on the subject go to www.sigcon.com

H.H.
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Old 5th March 2002, 11:48 PM   #4
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Default reset and ribbon cable

Hi Francois,

with the capacitor to ground, it will sometimes reset, sometimes I will have to do it manually. I think I will steal the reset signal that goes from the CD-player's control processor to the decoder chip. For a stand-anlone version, I will either provide space for a reset-chip or design something myself, i.e. resistor-capacitor combination with Schmitdt-trigger. I have not seen a home-made reset circuit on the web yet.

When all my design errors are corrected, I will make the pcb file available. It should also work with the AD1852 and 1855, the problem with the AD1852 being that you can only set the Sony 16 bit mode with a control processor.

You understood me correctly about the ribbon cable except that I use only one ground wire between each signal. But that should not make much of a difference to the impedance. Where did you obtain this information? Are you dealing a lot with HF stuff?

Greetings,

Eric (having just finished the bottle of Chateau La Vernède opened yesterday in celebration of the first sound)
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Old 6th March 2002, 03:28 AM   #5
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Default AD1854

Ribbon cable impedance:
http://www.sigcon.com/news/3_10.htm
http://www.daburn.com/~daburn/1888.html
http://www.altavista.com/sites/searc...nce&pg=q&kl=XX

Not too hard to find.........

H.H.
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Old 6th March 2002, 09:11 AM   #6
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H.H.,

Whatever we may need, HH has a link for it ! Thanks ! I'm amazed by the number of pertinent links you've posted 'til now. Impressive ! Keep it up !

Well, I do think too that signal integrity in digital audio designs is often overlooked. Maybe it's because it raises more questions than solutions . But, as you say, there are simple rules to improve the designs. Proper grounding and decoupling is now (almost) commonly accepted, but taking Zc into account and proper signal lines terminations is often left behind. I don't really understand why, since it's cheap, simple and effective... provided that you roughly know the dynamic output impedance of the IC's output pins

Just a few links about terminations :
http://www.pericom.com/docs/AB23.pdf
http://www.pericom.com/docs/AN22.pdf
(all Pericom's technical papers are worth a reading)
http://www.fairchildsemi.com/an/AN/AN-661.pdf

Many others can be found...

Eric "Red Wine" Capslock ,

I'm "usually" using two ground wires between signals. Only one wire doesn't modify impedance that much, but two wires improve shielding between signals. I first found this shielding/TL scheme on 3M's site (flat ribbon cables), but every cable manufacturer has now data on this.

Oh, and I do not usually deal with HF stuff. It's just that some of my school memories were awakened when I made the parallel between "fast rise time" and "PCB trace"
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Old 6th March 2002, 02:31 PM   #7
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Default signal integrety

In first approximation, ringing will not cause jitter. Reason: as nasty as the signals may look, all the pertubations should be reproducible, so unless the mechanics change (vibration of the cable, ...), each pulse should be the same.

Of course, when the signal is jagged at the transition voltage of the input, the exact time when the gate switches becomes non-deterministic. Also, noise injected into the DAC certainly won't do any good.

I will include 100 R series termination at the input to the ribbon cable. On the receiver side, I cannot use a 100 R to ground as this would increase the current draw and decrease the signal amplitude. I like to use 270 R series resistors, not as a termination but because it will filter out gunk on the signal line and isolate the DAC. This is for the BCLK, LRCLK and SDATA signals, which are supposedly not jitter sensitive.


I use a 74ALS04 to buffer the output of the oscillator before I send the clock signal into the cable to the CD transport. I was surprised at the amount of undershoot it produces even without a cable connected (-900 mV), but looking at TI app notes, this seems to be quite (not quiet) normal. Also, to my surprise, pk-pk jitter increased from 80 ps (oscilloscope intrinsic jitter) to about 130 ps after passing through two inverter gates. This is by no means better than a 74HCU04. However, this signal times the transport, so there should be no harm (assuming that the timing of the DAC is only controlled by the MCLK input signal that travels about 2 cm from the ECL oscillator and ECL-to-TTL converter to the DAC input pin.


Greetings,

Eric
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Old 8th March 2002, 12:01 AM   #8
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Default clock injected...

Just very quickly....

The ECL clock now gets injected into the CD player. Having lived with the new DAC and internal CD-player clock only for two days and not being able to do A/B-testing, I could be imagining things to a certain degree, but I would say the improvement is at least as big as installing the DAC in the first place.

So having a good clock vs. having an ok clock does make a HUGE difference. It appears much more pronounced than the change I observed when I replaced the clock on my Philips bitstream player, in spite of the fact that an SAA7350 should be much more jitter sensitve than an AD1854.

Eric
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Old 8th March 2002, 02:04 AM   #9
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Eric,
Would it be possible to make your schematic available too,
inclusive of the cable terminations you end up with and the
clock routing?

I had similar problems when I tried to pick the spdif signal
from my cd player (which did not have a cd digital out port)
pc board directly to my external dac that used the CS8414.
I made a direct connection. The signal would be intermittent.
I thought it was because the vlsi chip was not designed to
source that much current driving the capacitances of the
cable to the external dac.

Thanks for sharing your info.

rgds
Yv
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Old 8th March 2002, 08:10 AM   #10
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Default didn't do that...

There seems to be a misunderstanding. I did not use the digital out of the decoder chip. The signal comes out of the decoder's pin but there is no circuitry connected to it.

I simply tapped the BITCLOCK, LRCLOCK and SDATA connections.

For what you want to do, there must be plenty of description about how to add a digital output on the web. Easiest way: buffer signal with a a TTL F, ALS or ABT series chip, either a 04 inverter or preferably a bus driver like 540, 541. Use an output series resistor about 10 R smaller than the impedance of the cable you are using. Preferably, don't do that, use an output transformer.

Eric
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