Hi everyone
I found an interesting design of a dual ES9018 DAC. Unfortunately I couldn't get much information about the Board. Maybe take a minute to get a look:
FPGAÈí¿ØµÄË«²¢ES9018¸ßÉÕ½âÂë-ÌÔ±¦Íø
ÍíÀ´µÄË«²¢ES9018Ðø_µÚ¶þ°å - Powered by Discuz!
I tried to get in contact with the seller, who also claims to be the designer. Although we couldn't realy communicate (I don't speak chinese, and google translate is a pain), he convinced me to be involved in the engineering process.
My first thought on this was; could the ESS Chips maybe be feed by a synchronous master clock from the Cyclone FPGA? There is a discussion on this forum and as far as I know Weiss used a Dice chip to implement a synchronous master clock in their 202.
I asked him about this, but I think there were too many missunderstandings, so I didn't get a satisfying answer... I know, without any detailed insights, one can probably only speculate, but what do you think? Does it make sense, that a Cyclone FPGA is used to generate a synchronous master clock?
I found an interesting design of a dual ES9018 DAC. Unfortunately I couldn't get much information about the Board. Maybe take a minute to get a look:
FPGAÈí¿ØµÄË«²¢ES9018¸ßÉÕ½âÂë-ÌÔ±¦Íø
ÍíÀ´µÄË«²¢ES9018Ðø_µÚ¶þ°å - Powered by Discuz!
I tried to get in contact with the seller, who also claims to be the designer. Although we couldn't realy communicate (I don't speak chinese, and google translate is a pain), he convinced me to be involved in the engineering process.
My first thought on this was; could the ESS Chips maybe be feed by a synchronous master clock from the Cyclone FPGA? There is a discussion on this forum and as far as I know Weiss used a Dice chip to implement a synchronous master clock in their 202.
I asked him about this, but I think there were too many missunderstandings, so I didn't get a satisfying answer... I know, without any detailed insights, one can probably only speculate, but what do you think? Does it make sense, that a Cyclone FPGA is used to generate a synchronous master clock?
Just a small update. A closer look revealed, that indeed the MCLK is feed by the FPGA. Still I can't figure, if the master clock is synchronized with the bit clock (an exact multiple of it). I'll try to get in touch with WeiTone and ask again ... But anyway, what do you think of the board, is it worth a try?
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