Multi-frequency clock

[pieris]

mcs,

I looked at your schematic. Here are my recommendations.

The 1708 is probably a good compromise for complexity/performance. You might also consider the ICS661, or SM8701. The '661 only specs p-p jitter, which is completely different from the RMS jitter that the 1708 specs. So who knows which would sound better. Here is a paper showing tradeoffs of PLL versus discrete designs.

The regulator should be bypassed with 0.1uF as well as 10uF. The PLL seems to be lacking bypass caps also, definitely look at the ICS661 datasheet to see how they recommend adding bypassing caps. (0.01uF on each Vdd pin). Also, take care in laying out the crystal: surround the crystal traces with a copper fill (ground plane) to isolate them from digital signals. Make them narrow (for low C) and short.

Another issue is the clock accuracy. The exact frequency of the crystal is tuned by the load caps + stray capacitance. To get a precise clock with a discrete crystal, you'll need to use a frequency counter to see what frequency you're getting at the output, and adjust the load caps accordingly. Unfortunately, even at this point it will be temperature variant. You can avoid both these issues by using a precision 27MHz oscillator (like the CXOH from crystek). I highly recommend this option.

For power supply use a low-noise variety, like the MAX8510. You can actually daisy-chain a 5V and then a 3.3V part for better PSRR.

Many people on this forum (and elsewhere) like the idea of running a clock through a 7404 buffer. I think it's a bad idea to run a jitter-sensitive signal through a device that has absolutely no jitter characterization numbers. Two in a row will double your p-p jitter. In general, if no jitter numbers are given for a part, it has high jitter.

Instead of the 7404 I recommend a high-speed part designed for clock buffering. There are multitudes available from ICS, IDT, and Maxim. You can get 1:1 buffers or fanout buffers that have multiple outputs. They will add jitter but not as much as a logic part that was designed in the 1980's.

A neat idea is using a zero-delay buffer (this has an integrated PLL) as a jitter cleanup device, to follow a jittery signal. See the second app note listed on the page for the CY23FS08

You have no impedence matching. Check out this document on using back-matched resistors for high speed digital.

Have fun.
-Pieris

 

[mcs]

mcs,

I looked at your schematic. Here are my recommendations.

Thanks very much for your reply!

The 1708 is probably a good compromise for complexity/performance. You might also consider the ICS661, or SM8701. The '661 only specs p-p jitter, which is completely different from the RMS jitter that the 1708 specs. So who knows which would sound better. Here is a paper showing tradeoffs of PLL versus discrete designs.

It looks to me like the three chips have similar specs. But the PLL1708 is easy to control (because of the built-in serial port), and I also know where to buy it I have no idea how to get the others...

I will have a look at that document later (I'm at work now...).

The regulator should be bypassed with 0.1uF as well as 10uF. The PLL seems to be lacking bypass caps also, definitely look at the ICS661 datasheet to see how they recommend adding bypassing caps. (0.01uF on each Vdd pin). Also, take care in laying out the crystal: surround the crystal traces with a copper fill (ground plane) to isolate them from digital signals. Make them narrow (for low C) and short.

I know I need bypass caps. I mentioned that I left out the 117 bypass caps. I normally just draw a big group of caps somewhere on the schematic.

Another issue is the clock accuracy. The exact frequency of the crystal is tuned by the load caps + stray capacitance. To get a precise clock with a discrete crystal, you'll need to use a frequency counter to see what frequency you're getting at the output, and adjust the load caps accordingly.

Then the question is if my old HP frequency counter is accurate enough

For power supply use a low-noise variety, like the MAX8510. You can actually daisy-chain a 5V and then a 3.3V part for better PSRR.

That is my plan. The circuit will be powered by a low noise 5V supply, which then also serves as the input to the 3V3 regulator.

Many people on this forum (and elsewhere) like the idea of running a clock through a 7404 buffer. I think it's a bad idea to run a jitter-sensitive signal through a device that has absolutely no jitter characterization numbers. Two in a row will double your p-p jitter. In general, if no jitter numbers are given for a part, it has high jitter.

Are you sure the '04 adds any (serious amount of) jitter? I would think a simple buffer circuit may change the duty cycle slightly, which shouldn't matter as long as the change is constant. I planned on using single gates as I wrote, so I won't have problems with gates in a common package "disturbing" each other. Any other '04 opinions around?

Instead of the 7404 I recommend a high-speed part designed for clock buffering. There are multitudes available from ICS, IDT, and Maxim. You can get 1:1 buffers or fanout buffers that have multiple outputs. They will add jitter but not as much as a logic part that was designed in the 1980's.

A neat idea is using a zero-delay buffer (this has an integrated PLL) as a jitter cleanup device, to follow a jittery signal. See the second app note listed on the page for the CY23FS08

I will have a look at those buffers also.

You have no impedence matching. Check out this document on using back-matched resistors for high speed digital.

Another IDT app note lead me to believe that you only need impedance matching resistors on outputs driving long tracks/wires. Which is why I added 22R resistors on the buffer outputs, but not on the 1708 outputs that will only drive a few mm of PCB track. But adding them everywhere is not a big problem of course.

Best regards,

Mikkel C. Simonsen