DIR1703 spdif question

[jwagnerhki]

Hi,

I'm trying to get some sense out of TI's horrid DIR1703 datasheet.

To get the part to generate 96kHz and 512 fs, they tell in the "Selectable crystal oscillators" table that this works with an "external clock only".

Has anyone tried this?

Is it supposed to mean you have to add a 50MHz crystal oscillator to the input to the DIR1703? (though that wouldn't be any different from connecting any of the other crystal oscillators presented in the table, so, errm, huh..??)

Or does it mean add your own circuitry to generate ~50MHz and divide to 512 fs and 96kHz and generate all clocks externally, i.e. a complicated way of saying "not possible with the DIR1703"?

 

[ojg]

I have not tried this, but I think it means that you have to hook it up as shown on the right side of Figure 1 in the datasheet. In other words you can only use a 49.152MHz XO and not a 49.152MHz crystal.

 

[x-pro]

What is exactly you are trying to do with DIR1703? As SPDIF reciever it will ONLY output signals derived from whatever frequency it receives.

x-pro

 

[AD1865]

I have tryed DIR1703

It's useless to add 50M crystal oscillator. If you use 24.576M crystal oscillator and set 'SCF0' high and 'SCF1' high, then you must make 'BRSEL' opened, it will generate 512fs whatever frequence you input. If you use 11.2896M crystal oscillator, set 'SCF0' high and 'SCF1' low, then you must connect 'BRSEL' to 'EMFLG', it will generate 256fs whatever frequence you input. That means if you have selected crystal oscillator and system clock, you must make 'BRSEL' to correspond with.Then it will auto fit all the frequence(32k,44.1k,48k,88.2k,96k) and you need't change crystal oscillator.
My English is poor, but I hope it will not confuse you.

 

[Benjlv]

could someone explain to me what the 128fs...512fs are to me. I believe they have something to do with oversampling...

 

[jwagnerhki]

ojg:

In other words you can only use a 49.152MHz XO and not a 49.152MHz crystal.

Ok, all clear now! thx!!


And thanks ad1865. I'm still a bit confused though:

It's useless to add 50M crystal oscillator. If you use 24.576M crystal oscillator and set 'SCF0' high and 'SCF1' high, then you must make 'BRSEL' opened, it will generate 512fs whatever frequence you input. If you use 11.2896M crystal oscillator, set 'SCF0' high and 'SCF1' low, then you must connect 'BRSEL' to 'EMFLG', it will generate 256fs whatever frequence you input.

With a 24.576M crystal and SCF=(HI,HI), looking at table 3 this would allow receiving 96kHz SPDIF input and genearte a master clock of 256 or 128fs (96k*256=24.576M=max), or 88.2kHz @ 256 or 128fs, and for all <=48kHz it allows all 512 384 256 and 128fs. These x-fs can then be selected with the BRSEL pin. Right?

And with 11.2896M it can do 256fs, but ONLY at 44.1kHz and 32kHz, with BRSEL connected accordingly?

So I'd figure a ~50MHz external oscillator is still required to get 512fs when the SPDIF source clock is 96kHz?

Or am I still thinking wrong somewhere?

(verrry nice datasheet... *not*)

What is exactly you are trying to do with DIR1703? As SPDIF reciever it will ONLY output signals derived from whatever frequency it receives.

Allow it to receive 96kHz (max) SPDIF and still generate 512fs, running in "PLL mode". With no SPDIF signal, it should run in "crystal mode". It's the "tie UNLOCK pin to CKSEL" thing which is suggested in the dir1703 datasheet... 512fs because for the TAS3103 audio processor, a higher MCLK = more MIPS = good! The processor then drives a digital amp PWM stage.


thx

 

[AD1865]

I have confused you

Use 24.576M crystal oscillator, set 'SCF0' high and 'SCF1' high and make 'BRSEL' opened, you can receive any frequency, and need not change any set! DIR1703 can automatically receive any frequency and generate 512fs without any change on set.

 

[WTS]

Hi; Which DAR chip is the better one to use, the TI 1703 or the AD1892. I'm sure the Crystal ones could be in there as well, but you can't get samples of theirs now.

Thanks

 

[macboy]

The oscillator (whether crystal or XO) serves two purposes: it provides a clock reference to drive the SpAct circuitry which is used to reduce jitter in the clocks recovered from the S/PDIF input, and it also provides a means for the DIR1703 to generate a set of low-jitter clocks (MLCK, BCLK, LRCLK) in the absence of a S/PDIF signal, so that you can (for example) use an ADC as a source of your digital audio signal instead of S/PDIF, and clock it all using these clocks. The choice of oscillator frequency determines the frequency of these internally generated clocks.

 

[kirc]

some questions

Hi to all!

I'm trying to build my first dac using BB DIR1703 and PCM1728.
I have a lot of question about right frequency select on DIR1703.

I was read datasheet for DIR1703 for several time, but I still don't understand few things.

First of all. I'll like to build dac with 24bit and 96kHz compatibility.
If I use 24.576MHz crystal oscilator, set SCF0 to high, SCF1 to low, BRSEL to CSBIT and CKSEL to UNLOCK will my dac be able to receive any spdif frequency between 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz ? Is this correct ?

If I set DIR to I2S mode and 24bit output and the same mode on PCM - data will be trasmited correct, but I don't understand if this will work irrespective to input data which are 16bit from my CD57 ?

Sorry for my poor english.

Thanks for replay.