AD1862 PCB layout - diyAudio
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Old 3rd April 2014, 08:44 AM   #1
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Default AD1862 PCB layout

I'm in the process of making an AD1862 dac board and would like some input on how to separate analog and digital grounds.

I want to make a single ground plane as Guido Tent recommends, and use proper positioning of the the components to avoid the digital cicuitry creating noise on the analog ground. This is very easy with the AD1865 and the PCM63 chips, as the digital and analog parts inside the chips are neatly separated along the middle. But with the AD1862 it's not so easy. Looking at the datasheet it seems like the lower left part of the chip is used for digital, and the rest is analog. So how do I position two chips next to each other without mixing the grounds?

The only way I've managed to solve this problem is to make separate mono dac boards. I've created the circuit on a prototype board. It works fine with a mono board. Very low noise. But with two dacs side by side on one board, the left channel gets really noisy.

Any input on this subject is very welcome.
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Old 3rd April 2014, 12:41 PM   #2
marce is offline marce  United Kingdom
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No decoupling caps next to the power pins, especially on the digital side, some small package 100nF.
C1 C2 should be as data sheet C1 X10 C2s value.
You run the analogue out (P11) through the digital section!
Could you post your schematic and any mechanical constraints, as I think a complete rethink of the layout may be in order.
The analogue out, I would run as pseudo balanced to the next device in line (an op-amp?).
on site at the moment but will be at home at the weekend, have a bit of a layout to finish for someone else, then I will dig you out some practical examples of what I mean.
Marc
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Old 3rd April 2014, 01:19 PM   #3
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Quote:
Originally Posted by marce View Post
No decoupling caps next to the power pins, especially on the digital side, some small package 100nF.
C1 C2 should be as data sheet C1 X10 C2s value.
You run the analogue out (P11) through the digital section!
Could you post your schematic and any mechanical constraints, as I think a complete rethink of the layout may be in order.
The analogue out, I would run as pseudo balanced to the next device in line (an op-amp?).
on site at the moment but will be at home at the weekend, have a bit of a layout to finish for someone else, then I will dig you out some practical examples of what I mean.
Marc
Thanks for the quick reply!

The cap value choices are based both on sidiy's cd player project on diyhifi.org, and on Guido Tent's white paper on decoupling.

The 4,7uF and 47uF C1 and C2 are both in line with the recommendations in the datasheet; "The ratio between C1 and C2 should be approximately 10. Additional noise reduction can be gained by choosing slightly higher values for C1 and C2 (...)"

I have omitted the 100nF decoupling caps to avoid the ringing of parallel caps, shown in measurements here on the forum. This is also Guidos recommendation. But of course, I can experiment with some 100nF ceramics.

And then about the layout. I placed out all the caps first, in order to create the minimum return path from the supply pin to the respective ground pin. After that there was no other way to route the Iout trace. Is it that bad running the Iout trace between the VL+ and the TRIM pin?

The IV stage will be a discrete BJT, similar to Jocko and rbroer. Preferably on the same PCB. How would you implement a pseudo-balanced inteface? I have to admit I'm not even sure what you mean by pseudo-balanced in this case.

I'll post the schematic when I have access to it. As for mechanical constraints, there are none.

Any practical examples would be highly appreciated. I'm curious how you would rethink the entire layout.
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Old 3rd April 2014, 01:25 PM   #4
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Below is the hyperlink to an ADI app. note addressing this subject.

http://www.analog.com/static/importe...als/MT-031.pdf
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Old 3rd April 2014, 02:05 PM   #5
marce is offline marce  United Kingdom
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Sorry read the 4.7 as 47.
You need 0.1uF (MLCC, X7R preferably SMD) caps next to the power supply pins, as per the data sheet and common practice with all digital designs, in the smallest possible case. Without them you only have reservoir caps.
I can provide you with a whole host of information on decoupling....There is a lot more info out there since that was written, and clock speeds, rise times and just general density of PCBs has increased greatly in the last few years, as has EMC problems increased, it is an area I have studied quite intently over the last 28 years, as well as EMC.
As said earlier I am stuck on a customers site so cant do any practical examples till tomorrow/Saturday when I get back home.
I would be interested in a link to the ringing measurements you mention, it is not something that we see, and on most designs there are parallel capacitors, with varying degrees of value separation, sometime 1n, 10n 100n with larger reservoir capacitors (1uf to 100uf) placed in strategic locations.
Pseudo balanced means running a trace from the AGND pin next to the output pin from the convertor to the next stage, not using the ground plane for this critical connection (the AGND pin should be connected to the ground plane at the convertor), it will be easier to illustrate with a quick layout example, hence why I would like a schematic.
Are your signals going to be so low that you require adjustment?

One of, if not, the main man for EMC information, design recommendations:
http://www.hottconsultants.com/tips.html

I would recommend How to maximise your emissions, as a humorous guide on how not to do it...

Last edited by marce; 3rd April 2014 at 02:10 PM.
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Old 3rd April 2014, 03:32 PM   #6
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Wow! Thanks for the input. Your expertise is highly valued. And also thanks for the link.

I tried to locate the thread on this forum where someone had measured a lot of different coupling cap combinations, showing a lot of the common bypass arrangements creating a huge impedance peak at high frequencies. I only found this thread for now: paralleling film caps with electrolytic caps I believe it might be relevant as well. I'll continue to search for the measurements, and post them when i find them.

I understand the idea of partitioning the PCB into digital and analog sections. This is super easy for the PCM63 and the AD1865 with their interiors split at the middle. But the AD1862 seems to have something like a quarter of the interiors for the digital parts, which makes it harder to position the chips on the PCB, since it's a mono chip and you's need at least two chips.

I've attached the schematic. This is the actual circuit I'm listening to as we speak. I've made it on a prototype board with ground plane.

As for the MSB-trim I know Jocko Homo believes that it's mandatory, and he has a lot of experience with this chip. I get noise on the output when applying a -60dB test tone into the dac, with the amplifier at full level into 110 dB sensitive level. With the trim circuit I managed to adjust it until the noise disappeared. So I'd like to keep the trim option in the design.
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Old 3rd April 2014, 03:33 PM   #7
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Found the measurements:
Bypass cap measurements
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Old 3rd April 2014, 03:53 PM   #8
marce is offline marce  United Kingdom
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Slightly different to decoupling on PCBs, especially digital IC's, the PCB parasitics damp these resonances, as does using MLCC X7R decoupler's for the local caps.
Got to go for my train now so I'll be off line for a while 45hrs travel, no internet, I shall get back tomorrow.
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Old 3rd April 2014, 07:11 PM   #9
Eldam is offline Eldam  France
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painkiller,

Do you want to make two mono DAC with a common I2S ?
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Old 4th April 2014, 06:59 AM   #10
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Quote:
Originally Posted by marce View Post
Slightly different to decoupling on PCBs, especially digital IC's, the PCB parasitics damp these resonances, as does using MLCC X7R decoupler's for the local caps.
Got to go for my train now so I'll be off line for a while 45hrs travel, no internet, I shall get back tomorrow.
So putting 100 nF SMD ceramics as close to the pins as possible will be the way to go. At least for the digital line.

By the way, I've put a ground layer on the top of the board. All traces are on the bottom. So in the picture I provided in the first post the light green is the top ground plane layer, and the dark green traces are on the bottom layer.
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