Circuit wanted for a Low Phase noise 100MHz Clock

[JohnW]

Does anybody have a circuit diagram for a Low Phase noise 100MHz Clock with CMOS 5V output levels for a Digital Audio project I’m working on?

Short-term jitter is very important – not worried about the longer-term frequency drift.

I’m looking for close-in sideband noise better then –135dBc /Hz at 10Hz with better then –160dBc /Hz at 10KHz!

As a side note, be aware that standard High Frequency Clock modules above say 25MHz use PLL multipliers, typically X4 (Normally the ICS501 from Integrated Circuit Systems). These have very poor short-term Phase Noise performance typically 100pS RMS Jitter.

The last discrete oscillator I designed (very poorly) was a complete pain – hopefully someone out there has something better to hand…

Any help very much appreciated!

[ScottRHinson]

Originally posted by JohnW
Does anybody have a circuit diagram for a Low Phase noise 100MHz Clock with CMOS 5V output levels for a Digital Audio project I’m working on?

Short-term jitter is very important – not worried about the longer-term frequency drift.

I’m looking for close-in sideband noise better then –135dBc /Hz at 10Hz with better then –160dBc /Hz at 10KHz!

I would suggest reappraising the requirements for this part. I've helped design QAM-256 modulation equipment for the cable industry and the phase noise requirements you've listed are far stringent then required for that application.

A quick perusal of OCXO and VCXO type parts reviesl 10Hz offset phase noice in the -100dBc range...a far cry from -135.

Good luck.

Scott

[JohnW]

Hi Scott,

Thanks for your reply, your right that the specification requirements are very high, but I’ve just checked the specs for the HP10811A/B 10MHz Quartz Crystal Oscillator (this is an OVEN unit), and they quote –120dBc /Hz at 10Hz and –160dBc/Hz @ 10KHz. This unit is not renowned for its short-term phase noise.

The fact that this is an oven unit has very little to do with its short-term stability (Phase Noise) – but more to do with its Longer-Term Frequency Stability.

As I’ve said earlier, “Off The Shelf” commercial grade Crystal Oscillators, VCXO’s and OCXO’s are more often then not, based on IC oscillator / PLL building blocks - and as a result have poor Phase Noise performance - as you also have discovered and highlighted.

Simple discrete designs (based on Butler or Colpitts oscillators), while not possessing the Long-Term Frequency Stability performance, can be designed to meet the short-term Phase-Noise – at a consumer price point ($2 to $3).

To design reliable oscillators at this frequency is a “Black Art” and requires a fair deal of experience and understanding – far more then I well ever claim to possess!

I recently came across a design Application Note from National Semiconductors for a clock driver for one of their ADC’s. I was a simple 3 or 4 transistor design (100MHz or 125MHz), but typically, I cannot find it now I need it… (No, I’m not confusing it with the Analog Devices AN-419, which has poorer performance @ –110dBc /Hz).

Below is the Phase Noise result of a commercial 90.3168MHz “Low Phase Noise” Crystal module. This unit was based on an ICS501 x4 PLL.

Still holding out hope…

[Terry Demol]

Originally posted by JohnW
Does anybody have a circuit diagram for a Low Phase noise 100MHz Clock with CMOS 5V output levels for a Digital Audio project I’m working on?

Short-term jitter is very important – not worried about the longer-term frequency drift.

I’m looking for close-in sideband noise better then –135dBc /Hz at 10Hz with better then –160dBc /Hz at 10KHz!


Any help very much appreciated!

Hi Scott,

You will not find a 100MHz XO that can acheive -135dBc at
10Hz from carrier.
100MHz is not an optimal freq for low phase noise.
At 100MHz, even space qualified ultra low noise XO's won't
acheive -100dB at 10Hz. However they will acheive the
-160dBc noise floor at 10k
If you can drop to around 10MHz your specs are easily
acheivable and bettered... at a price.

Also, I'm not sure how these incredibly low phase noise
figures equate to sonics.

Perhaps better speak to Guido Tent one of the resident clock
experts.

Cheers,

Terry

[alvaius]

One thing to look at may be cooling an oscillator (or whatever you come up with). Phase noise (noise in general), generally drops with temperature, sometimes significantly.

Alvaius

[CheffDeGaar]

Long ago, I've built this XO (see image). Was used as a master oscillator for a DAC, and was operating near 98MHz. It performs quite well (sonically speaking), but never had the opportunity to measure the phase noise... No instruments It needs to be followed by another stage for 5V output. Personally, I've used a MC710ELT21 ECL comp, as per Analog's AN419, but flavours can differ here. If by any chance you build a version, I'd sure be interested by the phase noise figures . And if the NS AN you're looking for comes handy, let us know

By the way, I know that Elso have a 100MHz XO he uses for asynchronous reclocking, but he'll sure be wandering around here

[JohnW]

Thanks for replies.

First of all Pls. let me express my apologies to Scott if I’m wrong about being able to meet the Phase Noise requirements @ 100MHz with a crystal Oscillator.

Thanks to Cheff De Gaar, I will try his Oscillator design – when I can source the inductors.

Can anybody Pls. explain why it’s so hard to meet the Phase Noise requirements with a 100MHz Oscillator, and not with a 10MHz unit?

As an example, lets use the 10MHz HP10811D/E Opt 002 - which is guaranteed to be better then –133dBc /Hz @ 10Hz. Am I wrong it stating that the equation for Phase Noise scaling with frequency is: -

20Log (F2/F1)

So therefore a Super “100MHz HP10811D/E Opt 002” should have a Phase Noise at 10Hz offset of –113dBc / Hz?

Ok this figure is 22dB off my target, but its far better then most Low Phase Noise Oscillators modules I’ve found.

If a Crystal Oscillator cannot meet my target, what about LC or SAW Oscillators (not thinking about costs)?

Help - still tormented with Dynamic Range limitations due to Phase Noise!

[Terry Demol]

Originally posted by JohnW
Thanks for replies.

First of all Pls. let me express my apologies to Scott if I’m wrong about being able to meet the Phase Noise requirements @ 100MHz with a crystal Oscillator.

Thanks to Cheff De Gaar, I will try his Oscillator design – when I can source the inductors.

Can anybody Pls. explain why it’s so hard to meet the Phase Noise requirements with a 100MHz Oscillator, and not with a 10MHz unit?

As an example, lets use the 10MHz HP10811D/E Opt 002 - which is guaranteed to be better then –133dBc /Hz @ 10Hz. Am I wrong it stating that the equation for Phase Noise scaling with frequency is: -

20Log (F2/F1)

So therefore a Super “100MHz HP10811D/E Opt 002” should have a Phase Noise at 10Hz offset of –113dBc / Hz?

Ok this figure is 22dB off my target, but its far better then most Low Phase Noise Oscillators modules I’ve found.

If a Crystal Oscillator cannot meet my target, what about LC or SAW Oscillators (not thinking about costs)?

Help - still tormented with Dynamic Range limitations due to Phase Noise!

Sorry, my reply was to John not Scott.

John,

Why do you require such low phase noise? And what is
the application.

Cheers,

Terry

[JohnW]

Hi Terry,

I’m evaluating and characterizing Digital Modulators for a project I’m working on.

ZETEX ZXCW8100/6100 1MHz HPWM, MCLK 768Fs, 120dB Dynamic Range

ZETEX ZXCW8100/6100 2MHz HPWM, MCLK 768Fs, 124dB Dynamic Range *

NSP6000 MCLK 2048Fs 101dB Dynamic Range

TI5015 MCLK 2048Fs, 111.5dB Dynamic Range *

Sony CXD9634 (M65817AFP) 117dB Dynamic Range MCLK 1024Fs *

All the Dynamic Range results are Awtd.

* Results limited by Master Clock Phase Noise

At the lower Master clock frequencies, it’s been much easier to Generate a Low Phase Noise Clock; this gives the Zetex and Sony modulators an advantage. Standard oscillator modules at these lower frequencies tend to be simple discrete based designs. These simple designs achieve very good Phase Noise results – unlike the higher frequency PLL multiplier designs.

Despite the ZETEX’s better Dynamic range with 1MHz HPWM (with optimal output stage) it suffers from many faults: -

Very poor noise floor modulation at higher output levels – up to 15dB!

Very poor Third Order 19KHz & 20KHz IMD products @ -63dB, compare this to the TI at –115dB under the same conditions!

Due to faults in its modulation scheme, places a very high demand on the output stage performance.

And above all, poor sonic quality


The TI scores wonderfully, despite it only have a PWM rate of 8Fs, Shame it doesn’t have an inbuilt SRC or Gain / Tone functions.

The Sony CXD9634 (M65817AFP), has better Dynamic Range performance then the TI @ 117dB, but poorer 3rd Order 19KHz & 20KHz IMD of about –105dB. However, it does have a SRC and Gain Controls – but no tone features.

I’ve just received first silicon of an 8fs modulator (I’m under NDA, so I cannot reveal names), that has a theoretically 140dB dynamic range – at least in the digital domain. The limiting factors will be the external circuits – where the PWM signal becomes “Analogue”. The single biggest limiting factor will be the 2048Fs Master Clock.

Re-latching of the PWM data and Clock Generation and Clock routing to these latches will be done “Off Chip” to give the best chances of evaluating the performance of the Digital modulator section – so the reason behind my hunt for a “commercially priced” Low Phase Noise 100MHz Clock source solution.

[nemestra]

Originally posted by CheffDeGaar
Long ago, I've built this XO (see image).

For those of you looking for a reference and further information on the design of this circuit, it can be found in Appendix B of Robert J. Matthys' book, "Crystal Oscillator Circuits", Revised Edition 1992, Krieger Publishing Company, ISBN 0-89464-552-8

James