Any in depth testing / knowledge of the SM5872 DAC? - diyAudio
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Old 7th January 2014, 12:20 PM   #1
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Default Any in depth testing / knowledge of the SM5872 DAC?

Hi, I am in a fight modifying a couple of CD63's and a CD67SE
I need to completely understand the SM5872 DAC in order to arrive at a post dac filter solution and the datasheet is somewhat lean on actual info.

I do not like the solution of active conversion of it's digital output to analogue.

Initial tests seem to throw up some significant questions in my rather minutiae led mind.
Firstly, how is a ~1.44V common mode voltage exist at 50% modulation (Silence Level) when the digital output slews between 0-5V rails? In my mind, 50% modulation equates to 2.5V with a 5V rail.

I also measure a discrepancy in rise/fall time of the output signal with rise time of 8.2ns and fall of 6.6ns. In my mind, this skews the dynamic behaviour of the following filtering and differencing amp which would affect linearity at higher frequencies. It also points towards an imbalance in the impedances of the drive circuitry within the chip. This same issue is measurable in all of the players I have checked.

In addition, does anyone know the drive capabilities of the output drivers? I would like to filter passively, prior to buffering and amplifying etc. but designing filters accurately involves knowledge of the source impedances.

I have no doubt that this DAC is a very fine chip and is capable of great subjective sound quality but I'd like to realise it's full potential as well as understand it's idiosyncrasies so if anyone can advise on any articles/test data that could open the book on this device, I'd be very grateful.

Thanks

Last edited by db0360; 7th January 2014 at 01:19 PM. Reason: omitted word
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Old 7th January 2014, 10:33 PM   #2
guido is offline guido  Netherlands
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maybe rise/fall and drive could be "solved" by reclocking after the chip.

Crystal did this long ago with their CS4303 DAC chip. Checkout the CDB4303 document for the evaluation board of the thing. Not sure if you can find it on line, i've got it on paper.

They went to town with optocouplers, a pll and 74AC11074 latches.
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Old 8th January 2014, 12:11 PM   #3
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Thanks Guido, this sounds exactly what I'm looking for, thanks for the info but as predicted, can't find the info online. Is there any way you could scan the document and post it or email it to me please?

I'm still confused as to the 1.44V mid point given that the output swings rail to rail between 0 - 5V...any thoughts?

Dave
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Old 8th January 2014, 08:29 PM   #4
guido is offline guido  Netherlands
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Hi,

I can scan it somewhere in the near future. Planning to get me a new laser printer with build-in scanner. Sent me a pm.

As for the voltage, i don't know. Has been a while since i had a look at my cd63. It's streaming these days

I guess you need to have a look with a scope for starters. I can remember that the dac uses a number of fixed time periods between toggeling the output. So it is not just one time period with 50/50 on/off. It is four or six different periods, can't remember exactly. Should be something in the datasheet or on a forum. But still it should average to 2.5 i guess (?) unless the swing is not 0-5V. That you should be able to see with a a scope.

To look at the timing, i used an acient time interval analyser from Kode Odetics (which can do segmentation). But those things are rare.
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Old 9th January 2014, 09:54 AM   #5
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I have checked with a scope but my scope is USB Picoscope so it's not the greatest at recovering the kind of detail I need. However, it does confirm the voltages and rise times quite well.

I believe the chip has internal 2.8V logic probably derived from an internal regulator. This would be necessary as the chip is designed to function on 3.3V power so it would make sense that output mid rail would be around 1.4V. The outputs are probably derived from comparators referenced to the internal Vref but switched to external 5V rail.

My aim is to re-clock the outputs giving precision to the timing and with equal rise/fall times that are as fast as possible whilst eliminating bounce and ringing that currently exist. This would then make filtering simpler and more effective whilst offering precise signals to the first stage opamps.... I feel this is the best way to optimise the potential of the chip.

Prior research with amplifiers throws up serious failings in push pull amps that fail to operate around a precise mid point. Particularly distortions and linearity imbalances are severely compromised by offsets of DC. For this reason, I wish to present as balanced a signal as I can to the filter stages.

The thinking is that provided the technical operation of the decoding and conversion are optimised, then there is a sound, technically superior basic stage that can go on to be 'tuned' with caps, resistor types etc.

As my Mum used to say....you can't make a silk purse from a sow's ear!

Dave
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