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Old 3rd September 2013, 07:29 AM   #1
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Default TDA1543 semi-parallel solution

All parallel TDA1543 solutions have a shared Vref and a shared Analogue Out I/V resistor.
However, the TDA1543 also can work with a current source to achieve the same Vref as using a resistor to get the Vref.

So I have come up with a scalable solution for paralleling TDA1543's. In fact, it will be possible to insert one to many of these chips without changing any components

My trick to obtain this independence is by using a current mirror for the Iref pins of each chip; this current source (or dump as some might say) is running independent for each chip.
Likewise, on the output I do not sum the bias - I maintain separate I/V resistors, just to sum only the AC part with an array of coupling capacitors.

Each chip is now electrically isolated from each other (not the Vdd of course).

Questions I have:
  1. what is the fan-out of an XMOS I2S reciever? How many chips can be added without seriously deteriorating the output rise time? The TDA1543 is rather tolerant some say.
  2. Should there be a damping resistor like 5-10 ohms in the receving bus for each chip for CLK, WS, DATA? Some schema's use such.
  3. Or should I go for a buffer stage on the input bus (hope not).
  4. I now have two variables: Vdd and Iref. Or should I maintain variable I/V? Hope not, no place for trimmers
  5. I do have a distortion meter so I can see how to set the values and what effect they have on the distortion.
  6. I plan to go with mild oversampling in the computer to say 88.2 KHz and add a mild lowpass at 40-50 KHz of 6dB

What improvements do you suggest?

XMOS-parallel TDA1543.jpeg

albert
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Old 3rd September 2013, 07:48 AM   #2
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hi, thank you for your wonderful idea.

is l-out suppose to be tied to vref? and what benefit do you suppose there will be compared to ecdesign's solution of biasing rload resistors leaving vref floating?
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Old 3rd September 2013, 08:16 AM   #3
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Quote:
Originally Posted by PreSapian View Post
hi, thank you for your wonderful idea.

is l-out suppose to be tied to vref? and what benefit do you suppose there will be compared to ecdesign's solution of biasing rload resistors leaving vref floating?
Iout is independent of Vref because I still have a discrete I/V resistor, but several in parallel.
  • What is ECDesign's solution. Can you link to it?
Philips uses a floating opamp for I/V and this opamp is biased with the Vref. Actually just like a solution for the TDA151. However, just like with the stock solution, the DC point of the opamp output is not similar to the Vref (with the TDA1541 'Vref' is 0,0V) because there is current running through the I/V feedback resistor - and this implies distortion. Would however be 2nd harmonics if the difference is small; but imho the voltage difference is large between the two differential inputs (TDA1543: 2,5 mA*1k; TDA1541 2-4 mA*1k5).

So only with a current source this solution of an active follower with an opamp would work.
However with a FET follower (output connected to source) there would not be a problem with distortion because of a supplementary current. There would be a need for a separate bias for the fet.
Thinking about it, not a bad idea maybe, but I'd like to understand ecdesign's direction
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Old 3rd September 2013, 10:09 AM   #4
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In what way does using a current source per chip instead of a Vref resistor per chip improve things? Doesn't it just add a little noise and complication? You could still AC couple the outputs in parallel.
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Old 3rd September 2013, 01:09 PM   #5
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Originally Posted by DF96 View Post
In what way does using a current source per chip instead of a Vref resistor per chip improve things? Doesn't it just add a little noise and complication?
I'm not sure if the noise of a CS like this (e.g.. 2SC1815, 2SC2240) would make it worse in the internal CCS banks than a resistor with it's temperature noise.

Quote:
You could still AC couple the outputs in parallel.
The one advantage I look for is that I now can at my own choice add a chip or not without having to rebalance the whole thing.
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Old 3rd September 2013, 03:43 PM   #6
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Your CCS has resistors, typically of lower value than the Vref resistor would be. That means more thermal current noise. Plus transistor noise.

With a separate Vref resistor per chip, separate output resistor per chip and AC coupling, you can parallel as many chips as you wish.

It is not the CCS which allows you to parallel, but simply the fact that both Vref and output ports have 'per chip' arrangements and AC coupling.
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Old 4th September 2013, 06:46 PM   #7
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Agree,
for me a 390 resistor has lower noise than a 2K2, but indeed it is amplified.
Where would the 'noise' appear? In what is it visible do you think?
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Old 4th September 2013, 08:54 PM   #8
DF96 is offline DF96  England
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A 390 has less voltage noise than 2k2 but more current noise. Alternatively, in your circuit the voltage noise is amplified. Two different ways of looking at the same thing. You said you didn't want to use a resistor because of noise. I am just reminding you that your preferred solution has more noise. Probably still low enough, but I would not use a complicated circuit which has worse performance than a simple one - especially if the worse performance was in the very parameter I was worried about.
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Old 5th September 2013, 06:42 AM   #9
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OK, I agree on issues of complexity, and I tested yesterday with a resistor.
Aimed at 1,75 mA and with a certain Rout (variable, best 2k13) I got a nice 2nd harmonics, which is in phase. Too little: Iref bumps through the bottom (sags) and too high distorts at the other end. There is quite some latitude.
DCpoint of A out: 3,7-3,9 volt; at 3,5V it is least.
Vb=6,95 V
What I want to see next is if various chips have the same Iref/Rref combination. If so, I'll gladly keep it simple.

I will have to apply a 44 kHz filter though to get rid of the quantization steps that spoil the result of measuring.
Alternatively I need a 100 Hz 0 dB sine in large quantities (minutes on end) because my distortion meter has a steep 250 Herz filter.

First the central position,

Bart aug 2013 13 1.jpg

next the extreme of low with sagging,

Bart aug 2013 TDA1543 test L1020206.jpg

then the final choice with 2k13 and a higher 2nd.

Bart aug 2013 TDA1543 test L1020207.jpg


I have used the scope triggering; should use external triggering - that gives a better picture of the 'noise', now there is spurious flanks because of the steps.

Don't be baothered with the noise. It will disappear gradually. I promise!
albert
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Old 5th September 2013, 10:12 AM   #10
DF96 is offline DF96  England
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Quote:
Originally Posted by triode_al
What I want to see next is if various chips have the same Iref/Rref combination. If so, I'll gladly keep it simple.
There is bound to be a bit of variation. With a supply voltage at the upper end of the valid range you should have enough leeway to use a fixed resistor. At lower supply voltages it might need adjustment for each chip.

Have you seen my web page on passive I/V for the TDA1543?

Last edited by DF96; 5th September 2013 at 10:13 AM. Reason: typo
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