PCM1793 PCB Layout - diyAudio
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Old 16th August 2013, 08:30 PM   #1
Dr_EM is offline Dr_EM  United Kingdom
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Default PCM1793 PCB Layout

Hi all, just been designing a PCB for the TI DAC IC PCM1793. The datasheet specification is excellent and provided that spec can be met the DAC should offer exceptional performance at reasonable cost.

This design uses ultra low noise regulation for the analogue 5V rail, high PSRR 3.3V regulation for the digital section by a regulator stable with MLCC output capacitor. The Op-amp is one of the lowest noise types at modest cost with attractive specs all round (offset and input currents are important here). Regulated supply to the Op-amp is by LM317/337 pair set to +/-9V (easily enough to provide the full output this DAC is capable of).

The output filter/bal to SE converter is dimensioned to produce performance matching that in the datasheet, but using capacitor values available from the WIMA FKP2 range.


I hope that the layout can perform. I've tried to add local bypassing to each of the discrete 5V pins on the DAC, however I've not managed to return the bypass directly to the associated ground pin in all cases. Hopefully with the ground plane this is still sufficient? I believe the Vcom cap can be susceptible to noise; hence the smaller form factor film type being used here. Is there perhaps a benefit to bypassing it with a larger electro as well? The standard resistors in the filter circuit are to give flexibility in obtaining and matching the parts; the higher power rating may be welcome to reduce noise too.

A quartet of these may eventually be paired with my other board, the CS3318 volume controller:

CS3318 PCB Layout thread

Any input on optimising this design is welcome! Board costs are hopefully modest due to the small size (64x60mm).
Attached Images
File Type: png Mini DAC composite.png (130.0 KB, 426 views)
File Type: png Mini DAC top.png (105.7 KB, 415 views)
File Type: png Mini DAC bottom.png (97.5 KB, 400 views)
File Type: png Mini DAC schematic.png (47.6 KB, 417 views)
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Old 16th August 2013, 11:09 PM   #2
JensH is offline JensH  Denmark
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It is not possible to see on the pictures if you have vias close to the GND terminals of e.g. C25 and C29. I assume that there is a via here. Otherwise you will couple noise from the digital part into the analog part.

I would suggest to turn C25 (clockwise) and C29 (counterclockwise) by 90 degrees and connect the GND terminals directly to pins 8 and 9.
If you turn also C24 you can connect the GND directly to pin 19.

The 3.3V supply should probably be taken from C5 and not from pin 1 and 2 of the IC, but that is a minor thing.

I have only reviewed the design briefly. I would suggest to add via holes (if not already present) in a lot of places to connect the GND planes and minimize the loop lengths of decoupling paths.
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Old 16th August 2013, 11:45 PM   #3
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Your grounding is terrible.

On the bottom plane, ground has to travel all the way around the outside
of the board to get to inside.
On the top is not much better. Ground has to travel all the way around the LM317 and
the LM337 before getting to the inside.
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Old 17th August 2013, 08:01 PM   #4
Dr_EM is offline Dr_EM  United Kingdom
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Good input, some of it is quite glaring and I think I was a bit hasty posting the design, apologies.

The subtle, but hopefully much improved Rev1 is attached. I have re-orientated the capacitors and joined them to their respective ground where possible. I've excluded part of the ground fill (under the IC) so that digital ground returns to C29 before being bonded to the main ground surface, this feels like the right thing to do? Most improvements to the ground are simply by placing the GND header pin on the inside rather than outside but I've considered the various return paths and moved some tracks and added a few vias to hopefully keep impedance low. There's many through-hole components with a grounded lead around so this bonds the planes together at many locations as well. My main concern now is the +9V feed trace to the op-amp since the bottom side is quite broken up around here too.

Some other details on the design, data is I2S 24bit, I could add a jumper to select 16bit as an alternative but every device I've seen now produces 24bit and just pads 16bit data streams. Mute is unused, I plan muting upstream of this, and Reset is a simple RC affair, the Reset input is Schmitt action so this is fine to do. The DAC IC may be fully shutdown by connecting S/D to GND.
Attached Images
File Type: png Mini DAC composite Rev1.png (133.2 KB, 385 views)
File Type: png Mini DAC top Rev1.png (108.9 KB, 62 views)
File Type: png Mini DAC bottom Rev1.png (99.9 KB, 54 views)
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Old 17th August 2013, 09:28 PM   #5
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The grounding is much improved.

I'll go through it in more detail when I have more time.
Just time for a quick look right now.
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Old 18th August 2013, 11:43 AM   #6
marce is offline marce  United Kingdom
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Look at the connection from C8, move R8,R9 route this track through the middle of these restistors. You can then move the traces from the bottom layer that go to and from R10, 11, 12, 13, 14 IC2 C14 to the top layer. Look around the board and do this in other places. You want as few traces on the bottom layer as possible, and any that are left route so they do not cut the ground plane. Then add stitching vias between the top GND copper pour (it is not a plane) any Caps and GND pins to this bottom plane.
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Old 18th August 2013, 05:29 PM   #7
Dr_EM is offline Dr_EM  United Kingdom
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I see what you're saying, to basically strip away as much as possible from the bottom and use it as the ground return 'plane'. I've tried this out in Revision 2 (attached). The bottom fill is now very open in the centre and vias link the top to the bottom where there are grounded components with no local through hole ground link.

Thanks!
Attached Images
File Type: png Mini DAC composite Rev2.png (135.8 KB, 65 views)
File Type: png Mini DAC top Rev2.png (116.7 KB, 57 views)
File Type: png Mini DAC bottom Rev2.png (95.9 KB, 56 views)
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Old 18th August 2013, 06:06 PM   #8
marce is offline marce  United Kingdom
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Looks a lot better, well done. That's what PCB designs about, the more you do the more you can see the routing as you place the components. And having only two layers to play with really taxes the brain.
Another tip, leave a design alone for a day or so after you finish it, don't look at it or think about it, then go back and check it, you will always find something that you wonder why you did it like that or some area you can improve.

Glad to help.
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Old 18th August 2013, 10:49 PM   #9
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Ditto what Marce said.

Suggestions:

* Move the power connector next to the I2S connector. That would reduce the length of the VDD traces.

* Eliminate the S/D signal. Its intended use is to turnoff unneeded regulators to save power while a device is in standby mode. I donít see the need in your DAC. Mute is the proper signal to silence the DAC. Route MUTE to pin 10 of the I2S connector.

* Alternatively, route the DACís RESET signal to pin 10. Pulling RESET low has the same overall effect as shutting down the +5v and +3.3v regulators.

* Use a 6-pin power connector. Interleave VDD, VA+, and VA- with grounds and wire as twisted power/ground pairs.

* Every ground connection, including all SMDs, should have a dedicated via connecting the top and bottom ground pours. C9 has no via. Likewise pin 4 of the ADP3301. In other cases, such as C30, you rely on the ground of a nearby through-hole component. I prefer to overlap the via and the pad or connect the via to the pad with a short, no-clearance trace. That way, if sometime later I move the component, it is obvious the via has to move with it.
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Old 19th August 2013, 01:27 PM   #10
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Just another remark:
I'd try to change routing of +3V3 to pins 26 and 28 (FMT 0 and 2). The trace from R7 to the IC cuts ground returns of I2S signals!
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