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ftorres 19th February 2002 03:50 PM

ASRC Comparison ?
Hi there.

I was toying with the idea of a 24/192 capable DAC when I suddenly was faced by the upsampling question. I digged the problem just a little and ended up with a question : Which ASRC to use ?

I was thinking of the AD1896, but it needs glue logic to handle 192 kHz. You have to configure the chip in slave mode, generate the L/R clock and bit clock from the master clock. Moreover this master clock must be > 144fs (27.65MHz) and < 30 MHz.

Thus, I was thinking of a CS8420 for upsampling to 96 kHz, followed by a NPC SM5849 to upsample to 192kHz.

What would be your preference, based on jitter reduction and audio performance ? Has it already been tested ?


tiroth 19th February 2002 06:56 PM

What DAC are you using? I know that AD1852/3 simply oversamples to 384kHz for all inputs, so for 96kHz in it is 4X and for 192kHz it is 2X. I guess here it is a pick-your-poison issue of who you want to be doing the upsampling.

I am actually toying with AD1896->AD1853 at the moment, and will probably feed the DAC only 96kHz input as you lose considerable stopband attenuation at 192kHz. Of course, this means that I lose any jitter rejection of AD1896 if I feed it a 192kHz signal.

Norbert Bayer has tested AD1892 against CS8420 at 96kHz, but has not to my knowledge published his findings.


ftorres 20th February 2002 09:48 AM

Hi tiroth,

Thanks for replying.

I haven't yet chosen the DAC. I planning to test various ones (AD1853, PCM1730/38, maybe an AKM if I can get my hands on some...)

The 192 kHz working mode for the AD1896 isn't clear to me. The chip being set in slave mode, and starting from a L/R clock at 192 kHz, the bit clock must be 64 times higher (12.288MHz). OK. As in the evaluation board ( - page 7), the master clock is @ 24.576 MHz, thus 128 times the output sample rate. And it is stated in the datasheet that the master clock must be at least 138 times higher than the highest sample rate. Where did something go wrong ? If you chose a master clock @ 256 fs (49.152 MHz), you are far beyond the maximum MCLK (34 MHz). Thus, I don't clearly see here the relationship between the masterclock and the sample rate :confused: I surely miss something.

Concerning jitter rejection of the AD1896 @ 192 kHz, maybe that the external generation of L/R and bit clocks would be useful. The reclocking of all output signals is made easy with D flipflops, provided that I get a clear relation between MCLK and others :o Any help ?

Oh, and I'm not sure that the 1852/53 oversamples. In fact, I think it just interpolates internally.


tiroth 20th February 2002 02:55 PM

MCLK does not need to be syncronous to either the input OR output clocks in slave mode. 192kHz x 138=26.496 MHz, well under the 30 MHz limit. This creates a problem for generation of other clocks, though, as you point out that there is not a multiple of 128xFs that is <30 MHz. Likely this is why master mode is unsupported @192kHz-no easy divider.

You could have two clocks, one AD1896 MCLK, and one to generate the DAC MCLK, SCLK, LRCLK. Using AD1896 to reduce jitter at 192kHz is attractive to me, but I worry that in manually creating these clocks I would introduce more jitter than I would eliminate. Since I do not have equipment to measure jitter this is a real concern.

I believe this is the solution used on the AD1896 eval board, although I looked at the document very quickly. There is NOT a 24.576MHz crystal. The main clock is at 33.8688 MHz, and the 12.288MHz crystal is used only in slave mode, where all bitclocks and L/R clocks are externally provided.

Also, I am not sure why you make a distinction between upsampling/oversampling/interpolating. These are all the same.

ftorres 20th February 2002 03:33 PM

Hi back,

Thanks for your explanations, sounds much clearer to me.

As you pointed out, the presence on board of two clocks, one only for 1896 MCLK purposes, the other for clocking all the audio can raise problems (harmonic content), but I think it's worth a try. If I understand, the master clock in slave mode is only here to pace internal "computations". I'm not sure it has to be that clean (mainly from the jitter point of view). Pushing it to the limit, the internal oscillator can be used. The "main" clock, as rock steady as possible, will then be used to generate sensitive signals as you said (LRCK, BCLK, MCLK for DAC). You can use a high frequency clock, followed by various dividers, and reclock all the "low frequency" signals using the clock before they enter the DAC. I think this can be a nice way to reduce jitter.

Concerning eval board, look page 6 & 7. The on board 12.288MHz osc (u15) has to be replaced by a 24.576MHz one, which is not on board.

Thanks again for your help

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