FPGA + WM8741 and jitter

[marcomar82]

Hi,

I was thinking about driving the PCM input of a WM8741 DAC using the digital output lines of an FPGA based boarb.

The FPGA board has a shared FIFO memory with an embedded uC, so the uC load the wav data from a file to the FIFO memory and the FPGA convert them to PCM format and drive the WM8741 DAC.

I was just wondering about how good the digital signal from the FPGA is in terms of jitter. The oscillator on the FPGA board is 100ppm so I am worried this is not enough stable to guarantee a good sound.

Somebody has some tips/feedback about the architecture?

Do you think it would it be better to modify the board using a high precision oscillator?

Thank you
Marco

 

[Hugh Jazz]

Many variables affect jitter. It is not xo ppm (stability) alone. I am not designer so I cannot comment more. Maybe you can give more information and then the designer can help you.

 

[marcomar82]

Since FPGA are hardware coded, there shouldn't be any source of jitter, rather than the clock itself. Isn't it?

 

[glt]

Clock jitter depends on how the clocks are generated in the FPGA. These are additive to jitter of incoming clocks. The datasheets of the FPGA will have all the jitter specification.

No matter how you optimize, FPGA people will tell you that the minimum jitter in an FPGA is in the order of 100 psec of period jitter (which is the equivalent of 10-15 psec of phase jitter)

I'll say, don't worry about it. Improving the jitter coming out of a reasonable well designed FPGA will require a more sophisticate approach, for example Ian's FIFO reclocking board.

 

[abraxalito]

Agree with glt - the WM8741 has a switched capacitor output filter on-chip, rendering it as immune to jitter as a normal PCM style DAC. Your FPGA jitter is probably significant by audiophile standards but perhaps no worse than typically encountered over an S/PDIF interface.