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Old 28th December 2012, 09:14 PM   #21
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Location: Bradford
Simple inverse:
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File Type: jpg CXD1144iotiming.jpg (142.8 KB, 136 views)
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Old 28th December 2012, 11:39 PM   #22
Shinja is offline Shinja  Japan
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look closely the timing chart ,
in the DATA L row of I2S 8fs mode , it is annotated L1 R1 L3 above the chart.
and DATA R have R0 L2 R2 annotation.
it means the DATA L contains odd number of samples of 8fs signal and DATA R contains even.

one DAC of CDP-507ESD feeds the DATAL and WS/APT (and BCK),
the DAC outputs L1 and R1 at the next BCK from negative edge of WS/APT.
another DAC feeds DATAR and LE/\WS, then outputs L2 and R2 at the next BCK from negative edge of LE/\WS.
this is just the mechanism you presumed.
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Old 29th December 2012, 04:07 PM   #23
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Thanks, Shinja! I felt there should be an elegant solution.

I've never needed to understand a timing chart before, but in this case there's one pair of opposites too many for my head to grasp without an illustration.
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Old 1st January 2013, 07:08 PM   #24
nat8808 is offline nat8808  United Kingdom
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This idea went into Cambridge Audio's CD2, CD3 players and DAC3 (the original 80s one) didn't it but at x16 OS with 4 x 1541A chips? Or was it a different arrangment?

Have an advert somewhere that describes the arrangement in simplistic terms.

Stan Curtis says he spent time matching 1541As so that they were a closer match to each other than Philips provided with the S1s (probably custom matched Rs were too expensive to outsiders too ).
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