Hi,
I plan to build a DAC with my own design.
This dac is build around TI chips : PLL1705 + DIR1703 + SCR4192 + PCM1730
The PLL1705 generate the PLL clock for the DAC stage at 22.8792MHz.
In this case the receiver (DIR1703) is configurated in 512.fs and the SCR4192 in 128.fs to provide a 176.4 oversampling. The DAC PCM1730 has the same working mode as the output of the SCR4192.
The dac schematic is to big to be directly displayed on this page but you can view it with this following link:
DAC schematic
This plan represent only the DAC board, the I/V stage is not designed for the moment. I'm still working on it.
I'm not sure this DAC design is bugfree, I hope you can help me to make it so.
Alex
I plan to build a DAC with my own design.
This dac is build around TI chips : PLL1705 + DIR1703 + SCR4192 + PCM1730
The PLL1705 generate the PLL clock for the DAC stage at 22.8792MHz.
In this case the receiver (DIR1703) is configurated in 512.fs and the SCR4192 in 128.fs to provide a 176.4 oversampling. The DAC PCM1730 has the same working mode as the output of the SCR4192.
The dac schematic is to big to be directly displayed on this page but you can view it with this following link:
DAC schematic
This plan represent only the DAC board, the I/V stage is not designed for the moment. I'm still working on it.
I'm not sure this DAC design is bugfree, I hope you can help me to make it so.
Alex
Alex,
I'm designing a DAC around almost the same components as you and i'm thrilled to see that the schematics looks pretty much exactly as mine (only thing is that mine are still on a piece of paper
. I kind of lost myself in the power supply, voltage regulator and I/V stage which is some scary stuff for a electronics layman like me (i'm really into ebedded software), not to mention to figure out the outrageously complex PCB CAD my employer was kind enough to let me use on my free time.
Anyway, I choose to toss in the PLL1705 since I am planning to upsamle from 44.1 to 96kHz (i want to be able to hook in a DSP later on which only accepts 96KHz) and therefore need two clocks. Have you concidererd loosing the PLL1705, hooking up the crystal to the DIR1703 instead and let it drive the SRC4192/PCM1730 to 176.4kHz?
Henrik
I'm designing a DAC around almost the same components as you and i'm thrilled to see that the schematics looks pretty much exactly as mine (only thing is that mine are still on a piece of paper
. I kind of lost myself in the power supply, voltage regulator and I/V stage which is some scary stuff for a electronics layman like me (i'm really into ebedded software), not to mention to figure out the outrageously complex PCB CAD my employer was kind enough to let me use on my free time.Anyway, I choose to toss in the PLL1705 since I am planning to upsamle from 44.1 to 96kHz (i want to be able to hook in a DSP later on which only accepts 96KHz) and therefore need two clocks. Have you concidererd loosing the PLL1705, hooking up the crystal to the DIR1703 instead and let it drive the SRC4192/PCM1730 to 176.4kHz?
Henrik
Hi kirneH,
I choose the PLL1705 because it provide a good clock source and it’s easier and cheaper to by a 27Mhz crystal that a 11.2896MHz one. But an other solution is to use the DIR1701 instead of the DIR1703 because it use the same source clock ( 12Mhz ) for all input signal.
In first, I had designed an other DAC with two clocks with an upsampling from 44.1 to 192. But some people told me that 2 clocks are not a good idea because this can increase jitter effect.
old DAC shematic
Alex
I choose the PLL1705 because it provide a good clock source and it’s easier and cheaper to by a 27Mhz crystal that a 11.2896MHz one. But an other solution is to use the DIR1701 instead of the DIR1703 because it use the same source clock ( 12Mhz ) for all input signal.
In first, I had designed an other DAC with two clocks with an upsampling from 44.1 to 192. But some people told me that 2 clocks are not a good idea because this can increase jitter effect.
old DAC shematic
Alex
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