For SPDIF...
1. It does matter if you recover the clock - no matter whether you use it directly in you DAC or thru ASRC.
2. It matters a bit if you use some sort of FIFO, depends on nthe FIFO length and algorithms used.
3. It doesn't matter if you sync the transport from DAC's local clock oscillator.
So... 1 is still very popular, 2 is coming but rather rare AFAIK. 3rd one... A bit in the transport+DAC combos with propertiary interface.
1. It does matter if you recover the clock - no matter whether you use it directly in you DAC or thru ASRC.
2. It matters a bit if you use some sort of FIFO, depends on nthe FIFO length and algorithms used.
3. It doesn't matter if you sync the transport from DAC's local clock oscillator.
So... 1 is still very popular, 2 is coming but rather rare AFAIK. 3rd one... A bit in the transport+DAC combos with propertiary interface.
The consensus is that transport servo operation draws high current peaks, and this spoils analog PSU voltage, that affects DAC and analog signal output. Low mechanical jitter needs less servo correction, hence less current, less PSU noise. But I have never seen any objective experimental proof of this theory...
I find this thread interesting as the digital signal is generated in the transport from the zero crossing in the rf eye pattern coming off of the cd. If this eye pattern is indistinct due to jitter, it would seem to me that this error could never be corrected even with the most sophisticated reclocking schemes. I am not a digital theorist and would like someone who is to chime in. Thanks
The transport jitter is corrected by writing the digital stream into an elastic buffer, and reading out by the low-jitter master clock. The average clock frequency (and CLV - constant linear velocity) of the transport is controlled by a PLL, also synchronized to the master clock. The error signal of the PLL is the transport jitter.
Separate transport - DAC is a problem, because the SPDIF is a one-way link, the master clock is not fed back to the transport...
Reclockig cleans jitter occuring in the digital processing chain between the elastic buffer and the DAC chip - not the jitter occuring in the transport.
Separate transport - DAC is a problem, because the SPDIF is a one-way link, the master clock is not fed back to the transport...
Reclockig cleans jitter occuring in the digital processing chain between the elastic buffer and the DAC chip - not the jitter occuring in the transport.
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