CD master clock

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I am glad to sent my first message in audio.com and English is not my first language, please accept if my expression is not good .
I am using a China make Cd player-Cayin cdt-15A. I have done a few modifications: changed the film caps to old style oil caps, changed the op amp to AD627(ceramic package), changed the tube to Siemen gold pins E88CC etc. Last two nights I just changing the 2 master clocks in the CD.(Where the idea is just come from Audio.com) The player use two Master clocks, one is 16.9344 to drive SAA7327 (Vin is 3.3V), another is 24.576 to drive CS8420 (Vin is 5V) for 96kHz and 24 bit oversampling. I found a TCXO of 24.576 (1 ppm) and another general purpose XO of 16.9344 (50ppm) (just because cannot found TCXO at the moment). Both crystals powered by an 5V old dc-dc converter module made by Ericsson and decoupling by a few caps (1000u,2u,0.1,500p) and it worked fine at the beginning. Both dc voltage of the XO output are less than 5V, so there is no burning problem. Now the player is fine in run-in for about 36 hours and it will continue until 72 hours. The sound is great and the improvement is dramatical. I just want to say modifcation of the master clock is the most worthy to do so for a cd player and just want to share my experience.
 
Hi and welcome to the forum.
Elso and Guido among others will confirm your findings; but as I read your post (I know very little about clocks except they wake me up in the morning :D)
you changed almost everything in that player.
How are you so sure that the clock was the most improving?

Well, never mind, it simply must be fun to do and hear all these mods I guess. ;)

/Hugo
 
Thanks for your reply!
I changed the things one by one and every change give some solid improvement. The last one is the clock so the improvement is definely identified. Also this time the change is greater than the previous. The most valuable improvement is less loudness but more detials in high frequency, more air in vocal and high frequency hence less fragile to the ear. Smoother bass. Good resolution for some complicated records. ie. hear more that previous cannot hear. As a whole, listening is more comfortable and the sound is more noble. (My English is no good to explain in more detials)
By the way, modification is enjoying the result and also the process!
 
Masterclock

Hi ftp838,
Those 1 and 50 ppm are these jitterspecs or a frequency deviation spec?.
TCXO have generally better jitter specs but are harder to find and of course more expensive.
I would be curious to see how my clock compares to a precious TCXO. Can you disclose any source? I have given up knocking on crystal oscillator manufacturers doors......:headbash: :bawling:
 
:eek: Hi, Elso, thanks for your response.
The TCXO I got it from a local (Chinese)XO manufacturer. If my understanding is correct, the seller claimed it is 1ppm/degree C accuracy. (Actually I do not have the machine to verify this but only by listening). This manufacturer cannot suppy XO of 16.9344 as he told me his old engineer resigned and the new engineers cannot produce a within tolerance XO. (As you may know talents in China is precious at the moment) But 24.576 is within spec.
He will further to try to make some for me. The price is terribly low. (If you interested in the source please let me know and I will clarify and e-mail more info' to you)
 
Re: Masterclock

Elso Kwak said:
Hi ftp838,
Those 1 and 50 ppm are these jitterspecs or a frequency deviation spec?.
TCXO have generally better jitter specs but are harder to find and of course more expensive.
I would be curious to see how my clock compares to a precious TCXO. Can you disclose any source? I have given up knocking on crystal oscillator manufacturers doors......:headbash: :bawling:

dear all,

The unit of jitter is time

TCXO have better VLF jitter spec (tomorrows freq is about the same as today) but that is not relevant for sound quality (as long as it is within redbook spec)

1 out of 50 "standard" canned oscs is worth listening, but needs improvement

Low noise power supply is key !

regards
 
Hi,

can anyone tell me wich of the two master clocks in the CDT-15A has the greatest influence on sound quality?
A friend of mine want´s me to modify his player but doesn´t want to spent too much money. At the moment it´s not sounding very good on both solid state and tube output (grainy, not much air around the performers etc.)

thanks,

William
 
wuffwaff said:
Hi,

can anyone tell me wich of the two master clocks in the CDT-15A has the greatest influence on sound quality?
A friend of mine want´s me to modify his player but doesn´t want to spent too much money. At the moment it´s not sounding very good on both solid state and tube output (grainy, not much air around the performers etc.)

thanks,

William


the one that doesn't support the microcontroller

cheers
 
Hi Guido,

for digital dummies you´ll need to be a bit more specific.

As far as I know the CS8420 is an upsampler chip with digital in/out, reclocking by external clock.

Quote from Phillips website: "SAA7327 (CD7 II) is a single chip combining the functions of a CD decoder, digital servo and bitstream DAC, especially designed for Video CD applications. The decoder/servo part is based on the SAA737x (CD7) and is software compatible with this design. Extra functions are controlled by use of ‘shadow’ registers."

So I would guess that the last chip before the DA conversion is the most important (CS8420).
Does this mean that jitter in the path before the reclocking is unimportant or that I have absolutely no idea how this cd player works?

Many thanks,

William
 
I’m sorry to disagree, but the CS8420 is used as a SRC, and as such, the 24.576MHz (96KHz 256fs) clock is used as the secondary side master clock – which is also used to clock the DAC.

As this is the Master Clock (24.576MHz) to the DAC, this is the critical clock.

Any Phase Noise on the CD clock (16.9344MHz) is removed by the SRC. If the 16.9344 MHz clock was made 100% perfect, but the SRC clock poor, at the end of the day, the SRC clock performance dominates the results.

That’s not to say that the 16.9344 MHz clock is not important, as any dynamic frequency variation between the SRC input primary clock and SRC output secondary clock causes LF beating products due to isolation and ground plane / PSU coupling – but these effects are smaller then the effects of the secondary clocks Phase Noise performance.

I do however agree that the CS8420 sounds bad – I have a design where CD Data can be inputted directly in I2S or via CS8420 SPDIF / SRC, in both cases the Master clock remains the same (as the transport can be modified to except the DAC’s Master clock in I2S mode) – the difference is HUGE. Direct I2S is fair better.

I don’t know which DAC / Digital filter is used in your CD player, however if the Stop Band rejection of the DAC’s digital filter is poor, then adding an SRC (even the poor CS8420) can improve the audio performance - as you then gain the stop-band attenuation of the SRC which is normally greater then 120dB. In addition, the Phase Noise effect on Stop band attenuation is moved well above the audio band (google BENCHMARK Media Systems Inc, paper titled “Jitter & Its Effects”, Digital application Note #1).

The combination of these two effects is probably why “Upsampling” can improve the audio quality – but a well designed DAC / Digital filter with a low Phase noise clock will always sound better then an “Up-sampled” design, due to less digital processing.

John
 
JohnW said:

Any Phase Noise on the CD clock (16.9344MHz) is removed by the SRC. If the 16.9344 MHz clock was made 100% perfect, but the SRC clock poor, at the end of the day, the SRC clock performance dominates the results.

That’s not to say that the 16.9344 MHz clock is not important, as any dynamic frequency variation between the SRC input primary clock and SRC output secondary clock causes LF beating products due to isolation and ground plane / PSU coupling – but these effects are smaller then the effects of the secondary clocks Phase Noise performance.

I do however agree that the CS8420 sounds bad – I have a design where CD Data can be inputted directly in I2S or via CS8420 SPDIF / SRC, in both cases the Master clock remains the same (as the transport can be modified to except the DAC’s Master clock in I2S mode) – the difference is HUGE. Direct I2S is fair better.

I don’t know which DAC / Digital filter is used in your CD player, however if the Stop Band rejection of the DAC’s digital filter is poor, then adding an SRC (even the poor CS8420) can improve the audio performance - as you then gain the stop-band attenuation of the SRC which is normally greater then 120dB. In addition, the Phase Noise effect on Stop band attenuation is moved well above the audio band (google BENCHMARK Media Systems Inc, paper titled “Jitter & Its Effects”, Digital application Note #1).

The combination of these two effects is probably why “Upsampling” can improve the audio quality – but a well designed DAC / Digital filter with a low Phase noise clock will always sound better then an “Up-sampled” design, due to less digital processing.

John

wrong assumption

In theory that is what an SRC does, in practice it does not. Since it acts as an attenuator, it helps to reduce everyting you offer at the input, and my practice shows more can be gained at the drive side.

I agree that the upsampling clock is critical, but the upsampler adds so much jitter at the data output, that it, in turn, affects the DAC (on chip crosstalk), it helps to reclock all data at the output of the SRC.

A CS8412 with a decent secondary PLL and reclocking performs much better than a CS8420 alone. Ofcourse the latter is cheaper and easier to get away with.....

cheers

Guido
 
gentlemen,

I hope you can understand that I´m a bit confused by now:xeye:

I know that nothing is as simple as it seems but I´m looking at a way to modify (improve ) this player and would like to start by changing one clock. Either the 16MHz or the 24MHz.

The DAC after the CS8420 is a PCM1732J (HDCD). Is this clocked at 24 or 16Mhz?

William
 
Every SRC has a lower limit to its jitter attenuation abilities. I understand from conversations with the Crystal guys a while ago, that the CS8240 will reduce jitter on its Primary Master clock to about 3 pS. Below 3 pS, any phase noise is converted to an amplitude modulation error.

I don’t understand your comments about re-latching the data from the output of the SRC to the DAC. Why is jitter on the outputs of the SRC important (by Data - I presume you mean the DATA, BCK & WDCK)?

As an audio chip designer / consultant I can speak first hand when I say that a great deal of time is spent optimising the internal silicon layout with Guard-rails to prevent any cross modulation of the input DATA, BCLK & Word Clock before they are internally DOUBLE re-latched to the Master Clock. In this manner, only the phase noise of the Master clock (and PSU noise) can have any effect on the DAC’s operation in the time domain – jitter on the DATA, BCLK & LRCK can have no effect. In a well designed device, the PSU and ground pins to the devices internal input re-latching and internal clock distribution tree are kept completely isolated to prevent any issues.

Edge Ringing (overshoot and undershoot) should always be controlled on any input to a DAC / ADC. If left uncheck, i.e. poorly terminated, these voltage peaks can modulate the device substrate via the internal ESD protection diodes on the device pins & capacitively couple to other I/O’s. These ESD diodes clamp the I/O’s to the PSU pins, which have a finite impendence to the outside world / device decoupling. If you hear a difference by “re-latching” the data lines, then this is more likely to be caused by the reduction of edge ringing then any reduction in timing errors. Always correctly terminate all I/O’s – series termination with 100R is very effective for the serial DATA inputs (which can be slower), with say 27R for the Master Clock (which should be as fast a possible – but without significant ringing).

William,

Simple, what do you want: - lets say a good 5pS jitter clock clocking your CD transport section with a worst lets say 100pS clocking your DAC OR, a 100pS clock clocking your transport section (16MHz), and 5pS clock clocking the DAC (24MHz)!

True the SRC can only attenuate jitter (to about 3 pS), but ONLY if it has a good Secondary Master clock - in your case the 24MHz Clock.

As a chip and product designer, I would first improve the SRC secondary Master Clock (24MHz) – as this is what the DAC uses as its internal Master Clock - plain and simple.

The PCM1732 is clocked by the 24 MHz XO

John
 
JohnW said:
Every SRC has a lower limit to its jitter attenuation abilities. I understand from conversations with the Crystal guys a while ago, that the CS8240 will reduce jitter on its Primary Master clock to about 3 pS. Below 3 pS, any phase noise is converted to an amplitude modulation error.

I don’t understand your comments about re-latching the data from the output of the SRC to the DAC. Why is jitter on the outputs of the SRC important (by Data - I presume you mean the DATA, BCK & WDCK)?

As an audio chip designer / consultant I can speak first hand when I say that a great deal of time is spent optimising the internal silicon layout with Guard-rails to prevent any cross modulation of the input DATA, BCLK & Word Clock before they are internally DOUBLE re-latched to the Master Clock. In this manner, only the phase noise of the Master clock (and PSU noise) can have any effect on the DAC’s operation in the time domain – jitter on the DATA, BCLK & LRCK can have no effect. In a well designed device, the PSU and ground pins to the devices internal input re-latching and internal clock distribution tree are kept completely isolated to prevent any issues.

Edge Ringing (overshoot and undershoot) should always be controlled on any input to a DAC / ADC. If left uncheck, i.e. poorly terminated, these voltage peaks can modulate the device substrate via the internal ESD protection diodes on the device pins & capacitively couple to other I/O’s. These ESD diodes clamp the I/O’s to the PSU pins, which have a finite impendence to the outside world / device decoupling. If you hear a difference by “re-latching” the data lines, then this is more likely to be caused by the reduction of edge ringing then any reduction in timing errors. Always correctly terminate all I/O’s – series termination with 100R is very effective for the serial DATA inputs (which can be slower), with say 27R for the Master Clock (which should be as fast a possible – but without significant ringing).

William,

Simple, what do you want: - lets say a good 5pS jitter clock clocking your CD transport section with a worst lets say 100pS clocking your DAC OR, a 100pS clock clocking your transport section (16MHz), and 5pS clock clocking the DAC (24MHz)!

True the SRC can only attenuate jitter (to about 3 pS), but ONLY if it has a good Secondary Master clock - in your case the 24MHz Clock.

As a chip and product designer, I would first improve the SRC secondary Master Clock (24MHz) – as this is what the DAC uses as its internal Master Clock - plain and simple.

The PCM1732 is clocked by the 24 MHz XO

John


John,

Thanks for reply

Data jitter affects the on chip conversion clock. I know chip designers spend a great deal on optimising on chip clock jitter, but silicon is limitted.

Again, what you do not throw in, does not come out.

I agree on yor remark on termination (I like series resistors for more than one reason - http://www.tentlabs.com/Info/Articles/Supply_decoupling.pdf).

Modulation of the substrate however is caused by all I/O currents, not only those generated by clamping diodes.

On SPDIF: Jitter values up to 2 s can be found. If this jitter is reduced over 60dB (over the whole relevant jitter spectrum), one may assume that the conversion clock importance dominates. If not I still suggest to start at the drive.

Put in other words: I sell CD clock upgrades and DAC clock upgrades. The latter is more expensive while the first in general yields the biggest step forward.

After all, the proof is in the eating of the pudding: I offered William some support in finding out which clock is most worth to change first.

best regards

Guido Tent
 
JohnW said:
Simple, what do you want: - lets say a good 5pS jitter clock clocking your CD transport section with a worst lets say 100pS clocking your DAC OR, a 100pS clock clocking your transport section (16MHz), and 5pS clock clocking the DAC (24MHz)!

True the SRC can only attenuate jitter (to about 3 pS), but ONLY if it has a good Secondary Master clock - in your case the 24MHz Clock.

As a chip and product designer, I would first improve the SRC secondary Master Clock (24MHz) ?as this is what the DAC uses as its internal Master Clock - plain and simple.

The PCM1732 is clocked by the 24 MHz XO

John

John, the 24Mhz do not improve the sound quality too much, the 16Mhz is much more important, especially when you are not using the upsampling function of this CD-player.

Leo
 
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