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Old 25th March 2004, 11:22 PM   #11
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Hi ftp838,

I think this page can help you a bit, http://www.audioxtension.com/rev/CDT15A/cdt15a.htm

Leo
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Old 26th March 2004, 06:42 AM   #12
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Hi,

I saw this before I posted but I can´t read the text..........

William
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Old 26th March 2004, 04:34 PM   #13
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William

The 16.9344Mhz use for the transport, and the 24.476Mhz use for the upsampling, i think you should change the 16.9344 first, it the master clock of the cd-player.

Leo
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Old 27th March 2004, 11:39 AM   #14
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Quote:
Originally posted by f.k.l.chan
William

The 16.9344Mhz use for the transport, and the 24.476Mhz use for the upsampling, i think you should change the 16.9344 first, it the master clock of the cd-player.

Leo

Hi

I agree with this proposal

By the way, CS8420 is not my favourite.........

regards
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Old 27th March 2004, 05:16 PM   #15
JohnW is offline JohnW  Hong Kong
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I’m sorry to disagree, but the CS8420 is used as a SRC, and as such, the 24.576MHz (96KHz 256fs) clock is used as the secondary side master clock – which is also used to clock the DAC.

As this is the Master Clock (24.576MHz) to the DAC, this is the critical clock.

Any Phase Noise on the CD clock (16.9344MHz) is removed by the SRC. If the 16.9344 MHz clock was made 100% perfect, but the SRC clock poor, at the end of the day, the SRC clock performance dominates the results.

That’s not to say that the 16.9344 MHz clock is not important, as any dynamic frequency variation between the SRC input primary clock and SRC output secondary clock causes LF beating products due to isolation and ground plane / PSU coupling – but these effects are smaller then the effects of the secondary clocks Phase Noise performance.

I do however agree that the CS8420 sounds bad – I have a design where CD Data can be inputted directly in I2S or via CS8420 SPDIF / SRC, in both cases the Master clock remains the same (as the transport can be modified to except the DAC’s Master clock in I2S mode) – the difference is HUGE. Direct I2S is fair better.

I don’t know which DAC / Digital filter is used in your CD player, however if the Stop Band rejection of the DAC’s digital filter is poor, then adding an SRC (even the poor CS8420) can improve the audio performance - as you then gain the stop-band attenuation of the SRC which is normally greater then 120dB. In addition, the Phase Noise effect on Stop band attenuation is moved well above the audio band (google BENCHMARK Media Systems Inc, paper titled “Jitter & Its Effects”, Digital application Note #1).

The combination of these two effects is probably why “Upsampling” can improve the audio quality – but a well designed DAC / Digital filter with a low Phase noise clock will always sound better then an “Up-sampled” design, due to less digital processing.

John
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Old 27th March 2004, 05:53 PM   #16
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Quote:
Originally posted by JohnW

Any Phase Noise on the CD clock (16.9344MHz) is removed by the SRC. If the 16.9344 MHz clock was made 100% perfect, but the SRC clock poor, at the end of the day, the SRC clock performance dominates the results.

That’s not to say that the 16.9344 MHz clock is not important, as any dynamic frequency variation between the SRC input primary clock and SRC output secondary clock causes LF beating products due to isolation and ground plane / PSU coupling – but these effects are smaller then the effects of the secondary clocks Phase Noise performance.

I do however agree that the CS8420 sounds bad – I have a design where CD Data can be inputted directly in I2S or via CS8420 SPDIF / SRC, in both cases the Master clock remains the same (as the transport can be modified to except the DAC’s Master clock in I2S mode) – the difference is HUGE. Direct I2S is fair better.

I don’t know which DAC / Digital filter is used in your CD player, however if the Stop Band rejection of the DAC’s digital filter is poor, then adding an SRC (even the poor CS8420) can improve the audio performance - as you then gain the stop-band attenuation of the SRC which is normally greater then 120dB. In addition, the Phase Noise effect on Stop band attenuation is moved well above the audio band (google BENCHMARK Media Systems Inc, paper titled “Jitter & Its Effects”, Digital application Note #1).

The combination of these two effects is probably why “Upsampling” can improve the audio quality – but a well designed DAC / Digital filter with a low Phase noise clock will always sound better then an “Up-sampled” design, due to less digital processing.

John
wrong assumption

In theory that is what an SRC does, in practice it does not. Since it acts as an attenuator, it helps to reduce everyting you offer at the input, and my practice shows more can be gained at the drive side.

I agree that the upsampling clock is critical, but the upsampler adds so much jitter at the data output, that it, in turn, affects the DAC (on chip crosstalk), it helps to reclock all data at the output of the SRC.

A CS8412 with a decent secondary PLL and reclocking performs much better than a CS8420 alone. Ofcourse the latter is cheaper and easier to get away with.....

cheers

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Old 27th March 2004, 06:12 PM   #17
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gentlemen,

I hope you can understand that I´m a bit confused by now

I know that nothing is as simple as it seems but I´m looking at a way to modify (improve ) this player and would like to start by changing one clock. Either the 16MHz or the 24MHz.

The DAC after the CS8420 is a PCM1732J (HDCD). Is this clocked at 24 or 16Mhz?

William
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Old 28th March 2004, 12:51 AM   #18
JohnW is offline JohnW  Hong Kong
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Every SRC has a lower limit to its jitter attenuation abilities. I understand from conversations with the Crystal guys a while ago, that the CS8240 will reduce jitter on its Primary Master clock to about 3 pS. Below 3 pS, any phase noise is converted to an amplitude modulation error.

I don’t understand your comments about re-latching the data from the output of the SRC to the DAC. Why is jitter on the outputs of the SRC important (by Data - I presume you mean the DATA, BCK & WDCK)?

As an audio chip designer / consultant I can speak first hand when I say that a great deal of time is spent optimising the internal silicon layout with Guard-rails to prevent any cross modulation of the input DATA, BCLK & Word Clock before they are internally DOUBLE re-latched to the Master Clock. In this manner, only the phase noise of the Master clock (and PSU noise) can have any effect on the DAC’s operation in the time domain – jitter on the DATA, BCLK & LRCK can have no effect. In a well designed device, the PSU and ground pins to the devices internal input re-latching and internal clock distribution tree are kept completely isolated to prevent any issues.

Edge Ringing (overshoot and undershoot) should always be controlled on any input to a DAC / ADC. If left uncheck, i.e. poorly terminated, these voltage peaks can modulate the device substrate via the internal ESD protection diodes on the device pins & capacitively couple to other I/O’s. These ESD diodes clamp the I/O’s to the PSU pins, which have a finite impendence to the outside world / device decoupling. If you hear a difference by “re-latching” the data lines, then this is more likely to be caused by the reduction of edge ringing then any reduction in timing errors. Always correctly terminate all I/O’s – series termination with 100R is very effective for the serial DATA inputs (which can be slower), with say 27R for the Master Clock (which should be as fast a possible – but without significant ringing).

William,

Simple, what do you want: - lets say a good 5pS jitter clock clocking your CD transport section with a worst lets say 100pS clocking your DAC OR, a 100pS clock clocking your transport section (16MHz), and 5pS clock clocking the DAC (24MHz)!

True the SRC can only attenuate jitter (to about 3 pS), but ONLY if it has a good Secondary Master clock - in your case the 24MHz Clock.

As a chip and product designer, I would first improve the SRC secondary Master Clock (24MHz) – as this is what the DAC uses as its internal Master Clock - plain and simple.

The PCM1732 is clocked by the 24 MHz XO

John
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Old 28th March 2004, 09:05 AM   #19
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Quote:
Originally posted by JohnW
Every SRC has a lower limit to its jitter attenuation abilities. I understand from conversations with the Crystal guys a while ago, that the CS8240 will reduce jitter on its Primary Master clock to about 3 pS. Below 3 pS, any phase noise is converted to an amplitude modulation error.

I don’t understand your comments about re-latching the data from the output of the SRC to the DAC. Why is jitter on the outputs of the SRC important (by Data - I presume you mean the DATA, BCK & WDCK)?

As an audio chip designer / consultant I can speak first hand when I say that a great deal of time is spent optimising the internal silicon layout with Guard-rails to prevent any cross modulation of the input DATA, BCLK & Word Clock before they are internally DOUBLE re-latched to the Master Clock. In this manner, only the phase noise of the Master clock (and PSU noise) can have any effect on the DAC’s operation in the time domain – jitter on the DATA, BCLK & LRCK can have no effect. In a well designed device, the PSU and ground pins to the devices internal input re-latching and internal clock distribution tree are kept completely isolated to prevent any issues.

Edge Ringing (overshoot and undershoot) should always be controlled on any input to a DAC / ADC. If left uncheck, i.e. poorly terminated, these voltage peaks can modulate the device substrate via the internal ESD protection diodes on the device pins & capacitively couple to other I/O’s. These ESD diodes clamp the I/O’s to the PSU pins, which have a finite impendence to the outside world / device decoupling. If you hear a difference by “re-latching” the data lines, then this is more likely to be caused by the reduction of edge ringing then any reduction in timing errors. Always correctly terminate all I/O’s – series termination with 100R is very effective for the serial DATA inputs (which can be slower), with say 27R for the Master Clock (which should be as fast a possible – but without significant ringing).

William,

Simple, what do you want: - lets say a good 5pS jitter clock clocking your CD transport section with a worst lets say 100pS clocking your DAC OR, a 100pS clock clocking your transport section (16MHz), and 5pS clock clocking the DAC (24MHz)!

True the SRC can only attenuate jitter (to about 3 pS), but ONLY if it has a good Secondary Master clock - in your case the 24MHz Clock.

As a chip and product designer, I would first improve the SRC secondary Master Clock (24MHz) – as this is what the DAC uses as its internal Master Clock - plain and simple.

The PCM1732 is clocked by the 24 MHz XO

John

John,

Thanks for reply

Data jitter affects the on chip conversion clock. I know chip designers spend a great deal on optimising on chip clock jitter, but silicon is limitted.

Again, what you do not throw in, does not come out.

I agree on yor remark on termination (I like series resistors for more than one reason - http://www.tentlabs.com/Info/Article...decoupling.pdf).

Modulation of the substrate however is caused by all I/O currents, not only those generated by clamping diodes.

On SPDIF: Jitter values up to 2 s can be found. If this jitter is reduced over 60dB (over the whole relevant jitter spectrum), one may assume that the conversion clock importance dominates. If not I still suggest to start at the drive.

Put in other words: I sell CD clock upgrades and DAC clock upgrades. The latter is more expensive while the first in general yields the biggest step forward.

After all, the proof is in the eating of the pudding: I offered William some support in finding out which clock is most worth to change first.

best regards

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Old 28th March 2004, 08:44 PM   #20
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Quote:
Originally posted by JohnW
Simple, what do you want: - lets say a good 5pS jitter clock clocking your CD transport section with a worst lets say 100pS clocking your DAC OR, a 100pS clock clocking your transport section (16MHz), and 5pS clock clocking the DAC (24MHz)!

True the SRC can only attenuate jitter (to about 3 pS), but ONLY if it has a good Secondary Master clock - in your case the 24MHz Clock.

As a chip and product designer, I would first improve the SRC secondary Master Clock (24MHz) ?as this is what the DAC uses as its internal Master Clock - plain and simple.

The PCM1732 is clocked by the 24 MHz XO

John
John, the 24Mhz do not improve the sound quality too much, the 16Mhz is much more important, especially when you are not using the upsampling function of this CD-player.

Leo
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