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Old 22nd October 2003, 05:40 PM   #1
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Default Reclocking the SPDIF line

OK, I've read the posts regarding just transfering the direct I2S lines from the decoder via some coax cables. This has merit, but I'd like to try to go another direction with reducing the jitter problems associated with SPDIF.

Elso, you have noted that (for example) the PCM1716 datasheet states that it can be used with an independent "stand alone" crystal oscillator. You further note that most delta-sigma DAC's are capable of this as well... and I've read this now a few additional places.

I have some questions regarding this:
1. I'm assuming that by creating a new master clock, one would also clock-divide this to produce the bit clock and word clocks... so that they are all syncronous to each other. Correct assumption?
2. How can one have the data line itself asynchronous to the clocking lines?
3. Wouldn't the data line itself have some inherent jitter in it as well?
4. Would a delay of some sort need to be added to the master clock to keep it in sync with the clock-divided bit and word clocks?
5. Does anyone have a simplfied conceptual diagram of this type of topology?

Many thanks for your thoughts...
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Old 22nd October 2003, 06:52 PM   #2
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Default Re: Reclocking the SPDIF line

Quote:
Originally posted by Tieftoener
OK, I've read the posts regarding just transfering the direct I2S lines from the decoder via some coax cables. This has merit, but I'd like to try to go another direction with reducing the jitter problems associated with SPDIF.

Elso, you have noted that (for example) the PCM1716 datasheet states that it can be used with an independent "stand alone" crystal oscillator. You further note that most delta-sigma DAC's are capable of this as well... and I've read this now a few additional places.

I have some questions regarding this:
1. I'm assuming that by creating a new master clock, one would also clock-divide this to produce the bit clock and word clocks... so that they are all syncronous to each other. Correct assumption?
2. How can one have the data line itself asynchronous to the clocking lines?
3. Wouldn't the data line itself have some inherent jitter in it as well?
4. Would a delay of some sort need to be added to the master clock to keep it in sync with the clock-divided bit and word clocks?
5. Does anyone have a simplfied conceptual diagram of this type of topology?

Many thanks for your thoughts...
Hi Tieftoner,
Ough, a lot of intrigueing questions I hardly know the answer of.
First let me say it was just an idea to use an asynchronous clock with a Delta-sigma DAC. I do not have such a DAC so I will not perform this experiment. I am not aware of the inwards of the chip of a deltasigma dac and digital filter. Maybe the synchronizing is just done as in my asynchronous recloker with two flip-flops in series or even with a more sophisticated scheme as found on the net.
So quite frankly I do not know. Just try it and see if it works.
For me the best appoach seems to be not to mess around with the digital signals hence the I2S direct idea. Not invented by me, but Audio Alchemy, Sonic Frontiers, Northstar and others are using it.
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Old 22nd October 2003, 07:16 PM   #3
OliverD is offline OliverD  Germany
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Default How to (almost) elmiminate the jitter problem

To adress the jitter problem, you have to know which clock signal of your DAC is responsible for the actual change of the analog output signal between two samples. I'm using the PCM1704 and for this chip it is the bit clock signal. For you, this might be a different signal, but it is not the data line. See the datasheet of your chip.

If you get this clock signal as low-jitter and clean as possible, the jitter problem is almost eliminated as timing inaccuracies of the other clock or data lines won't show up at the analog output of the DAC. To further isolate clock signals from the DAC and analog circuitry, it is a big advantage to have dedicated clock, digital and analog power supplies. The grouding scheme is also very important.

This approach implies a local, independent clock source near the DAC. To resolve the synchronization problem, either clock the digital source (CD transport or whatever) from this local oscillator, or, if you're using S/PDIF, use an ASRC at the input of the DAC.

My digital preamp uses a CS8420 ASRC, DF1704 digital filter and PCM1704 DAC chipset. The bit clock of the PCM1704 is directly driven from the Kwak clock, the rest of the circuit gets the inverted output of the Kwak clock. This setup sounds excellent and you can hear almost no difference whether the digital source is a high quality CD transport or a cheap computer CD-ROM drive.
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Old 22nd October 2003, 08:07 PM   #4
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AMT-freak,
Thanks, that's some VERY helpful information... and very (obviously) good point about the bit clock moving the analog signal value. I'll be sure to double check the datasheet on the DAC I choose to use (most likely going to be the CS4396 at this point).

All along, I've been trying to figure out how to integrate the Kwak Clock to an external DAC... and this now alleviates some major issues. And it even makes sense

You say that the bit clock of the PCM1704 DAC is fed directly from the output of the Kwak clock... but what feeds the input of the Kwak clock? The bit clock output of the DF1704?

How do you dirive the word clock? Clock divide the Kwack clock output?

What do you mean by: "...the rest of the circuit gets the inverted output of the Kwak clock."????

Sorry about the many questions - I'm just trying to understand
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Old 22nd October 2003, 08:35 PM   #5
OliverD is offline OliverD  Germany
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Sorry about not being clear.

The CS8420 decouples input (S/PDIF) and output (I2S) clocks completely. No matter what input sampling frequency the CS8420 receives via its S/PDIF input, it will output 96 kHz I2S signals. To achieve this, it needs an independant 24.576 MHz input clock (256 x sampling frequency).

To generate this clock signal, I use the Kwak clock with a fundamental mode 24.576 MHz crystal. The Kwak clock has no input as such besides power supply, as all circuitry after the CS8420 is asynchronous to and independant from the input signal's clock and timing.

The standard approach would be to feed the CS8420 output signals to the DF1704 (glueless interfacing possible) and from there to the two (or four in my DAC) PCM1704s. Both CS8420 and DF1704 would be clocked from the Kwak clock output. This way, the low-jitter Kwak clock signal would pass through a couple of gates in the DF1704 before entering the PCM1704.

However, by a very helpful coincidence, the bit clock of the PCM1704 in my application is also 256 x fs = 24.576 MHz. So I simply leave the DF1704's bit clock output alone and instead directly connect the Kwak clock's output to my DACs, shortening the clock signal path and bypassing some gates. The word clock still comes from the DF1704, but as mentioned in the previous post, it will not affect the timing of the analog output. There is only one caveat: To synchronize the parts properly, CS8420 and DF1704 need a clock signal of inverse polarity compared to the PCM1704. This is no problem at all as the Kwak clock has inverting and non-inverting outputs anyway.

My scanner is not working properly at the moment, but if more clarifaction is needed, I will draw a simplified schematic and try to post it somehow.

Feeding the DAC's bitclock directly from a low jitter clock with separate power supplies is about the best you can achieve. There is one problem though. The ASCR will not output exactly the same digital signal that is read from CD or DVD (obviously when input and output sampling rate differ, but also when input and output clocks are out of sync).

BTW, the designer of the JISCO device mentioned in another thread claims that ASCRs super-impose the transport's jitter on the digital signal, a claim which I do not agree to, but that's a different matter. The statement probably helps to sell a couple of logic chips for 500 bucks

Jisco thread is here:
JISCO Jitter reduction
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Old 23rd October 2003, 09:15 PM   #6
OliverD is offline OliverD  Germany
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Relevant clock and digital signal connections of the DAC described above:
Attached Files
File Type: zip dac-clock.zip (23.5 KB, 774 views)
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Old 24th October 2003, 06:29 PM   #7
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Vielen dank!!
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Old 24th October 2003, 07:43 PM   #8
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I'm going through the CS8414 DIR spec sheet again, as I already have 5 or 6 of them, so my first DAC is going to use it. I can always make improvements later, which I most certainly WILL do

I have had a revalation... perhaps

First off, Cirrus likes to call the bit clock "SCK". I was looking at the Crystal CDB4396 (eval board for CS4396/7 DACs) as a reference for designing my version, and realized that they don't have any reset switch setup for the CS8414 on board. This lead me to the CS8414 data sheet. To put the CS8414 in reset, one has to put all four mode pins (M3-M0) high. In looking further at the "special modes" table, there is a mode for using an Asyncronous SCK input. "INTERESTING..." I thought outloud...

Does this mean that I could send a low jitter SCK source (Kwak clock) in to the SCK of the CS8414??... thus giving me the ability to use SPDIF, and readily get a low jitter signal to send to the DAC? On page 21 of the data sheet, it describes this mode as format 11, saying:
Quote:
"Format 11 is silmiar to format 0 [L/R, 16-24 bits mode, not I2S] except that SCK is an input and FSYNC [left/right clock] is an output. In this mode FSYNC and SDATA are synchronized to the incoming SCK, and the number of SCK periods between FSYNC edges will vary since SCK is not synchronous to received data strream."
Say, I just want this outboard DAC to decode red-book CD standard, is there any reason I couldn't generate a low-jitter bit-clock (SCK) for a 44.1kHz fs? I'm assuming this would just be the standard 256fs, thus 11.2896MHz. In my head, this seems to make sense. I'm just confused as to why they first say that the FSYNC and SDATA are synchronized to the incoming SCK, but then they say that there will be a varying amount SCK periods between FSYNC edges. That doesn't make sense to me...

Any help would be greatly appreciated!! Thanks,
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Old 24th October 2003, 07:59 PM   #9
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Quote:
Originally posted by Tieftoener
I'm going through the CS8414 DIR spec sheet again, as I already have 5 or 6 of them, so my first DAC is going to use it. I can always make improvements later, which I most certainly WILL do

I have had a revalation... perhaps

First off, Cirrus likes to call the bit clock "SCK". I was looking at the Crystal CDB4396 (eval board for CS4396/7 DACs) as a reference for designing my version, and realized that they don't have any reset switch setup for the CS8414 on board. This lead me to the CS8414 data sheet. To put the CS8414 in reset, one has to put all four mode pins (M3-M0) high. In looking further at the "special modes" table, there is a mode for using an Asyncronous SCK input. "INTERESTING..." I thought outloud...

Does this mean that I could send a low jitter SCK source (Kwak clock) in to the SCK of the CS8414??... thus giving me the ability to use SPDIF, and readily get a low jitter signal to send to the DAC? On page 21 of the data sheet, it describes this mode as format 11, saying:

Say, I just want this outboard DAC to decode red-book CD standard, is there any reason I couldn't generate a low-jitter bit-clock (SCK) for a 44.1kHz fs? I'm assuming this would just be the standard 256fs, thus 11.2896MHz. In my head, this seems to make sense. I'm just confused as to why they first say that the FSYNC and SDATA are synchronized to the incoming SCK, but then they say that there will be a varying amount SCK periods between FSYNC edges. That doesn't make sense to me...

Any help would be greatly appreciated!! Thanks,
Hi Tieftoner,
These Cirrus/Crystal datasheets are wrote by a individual coming from Mars. Totally incomprehensible.
I have good reason to believe Doede is right but I prefer I2S direct as we omit a lot of messing around with digital signals.
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Old 24th October 2003, 08:51 PM   #10
OliverD is offline OliverD  Germany
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Default More about reducing jitter

Two address the jitter problem, there are five "standard" ways, all of which have been implemented commercially and DIY.

1.) Get rid of the problem right at the source, e.g. the player. The player and the DACs would be fed from the same local low-jitter clock. PSU design and clock distribution scheme would be optimized to have the lowest jitter possible at the DAC, while the jitter at the rest of the circuit isn't that important.

For external DACs, we either have to isolate the timing of incoming signal from the timing of the DAC chip, or recover the original clock better than usual.

2.) Design a high quality PLL which recovers the original clock better than a simple CS841x receiver chip. The Pass Labs D1 (service manual available from their site) is a nice example of a good implementation of this technique.

3.) Let the input data stream fill a FIFO buffer. The DAC is fed from a local low-jitter clock and the data comes from the buffer. Due to the separate transport and DAC clocks, the buffer will empty or fill up slowly, depending on which clock is faster. Thus, we must provide some means to slightly "tune" the local clock source to keep the buffer about half filled.

4.) Use an ASRC to complete isolate the timing of input data stream and DAC chip. This approach is cheap and easy, but there are some caveats.

5.) Asynchronous reclocking right before the DAC. A nice idea, cheap to implement and it works good.

@Tieftoener, unfortunately I don't think your idea will work, because the CS8414 neither contains memory nor an ASRC.
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