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Old 19th August 2012, 06:48 AM   #1
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Default XMOS BAD sound?

I just purchased the offical XMOS audio 2.0 evm and using an oscilloscope to view the i2s mck sck etc. But I found that there is a serious delay between each signal rise edge replacing the default crystal circuit with a high quality oscillator without help.

There is overhead to process the USB signal, but the MCK is directly route from the crystal/oscillator, result: they are not in syn anymore. I don't think there is a DAC can process this kind of out of phase I2S signal good.
The MCLK must syn with the I2S data before processing with other DAC.
Any xmos design already exist with syn'ed i2s, I am a lazy guy

I am also surprise to found out that even the decade old PCM2707 I2S out wave form from CRO is far better than then the XMOS I2S, is the asyn 2.0 only a marketing strategies
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Old 23rd August 2012, 10:54 AM   #2
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I just try another USB 2.0 audio chip CM6631 to I2S interface,
same delay problem
But I am surprise to see that the old PCM2707 has the best sync signal
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File Type: jpg pcm270x44k1.jpg (37.8 KB, 305 views)
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Old 24th August 2012, 01:51 AM   #3
1audio is offline 1audio  United States
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Quote:
Originally Posted by wizard1238 View Post
I just try another USB 2.0 audio chip CM6631 to I2S interface,
same delay problem
But I am surprise to see that the old PCM2707 has the best sync signal
Usually you want the data stable for a certain period (setup time) before the clock or there is a race condition inside the chip. Having the data change with the clock leaves a serious question of whether the clock caught the correct edge of the data. Changing the data on the "back side" of the clock is considered the best practice.
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Old 24th August 2012, 02:22 AM   #4
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Have you checked to see if the bit clock, LR clock and data streams are synchronous or not? Lots of modern DACs only require that the master clock be at an exact multiple of the sampling frequency, not that the clocks are synchronous too.

I mean obviously the bit clock, LR clock and data streams have to be synchronous as this is how the raw data is clocked into the DAC chip. I am assuming that those clock lines are synchronous.
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Old 24th August 2012, 01:42 PM   #5
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Hi wizard1238

Just have seen Your posts.
Could You check BitClock on Your XMOS board, with the same scope set-up as mine.
Just set trigger at rising edge and move waveform on the screen to see the falling edge of BitClock.
Please have a look at my screens.

Rosendorfer
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File Type: jpg BitClock_2ns.jpg (355.9 KB, 268 views)
File Type: jpg BitClock_5ns.jpg (352.2 KB, 257 views)
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Old 24th August 2012, 01:44 PM   #6
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Hi

Forget to mention, You need to set Your probe to x10...
And to turn persistence to infinite .

Rosendorfer

Last edited by Rosendorfer; 24th August 2012 at 01:56 PM.
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Old 28th August 2012, 10:19 AM   #7
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Quote:
Originally Posted by Rosendorfer View Post
Hi wizard1238

Just have seen Your posts.
Could You check BitClock on Your XMOS board, with the same scope set-up as mine.
Just set trigger at rising edge and move waveform on the screen to see the falling edge of BitClock.
Please have a look at my screens.

Rosendorfer
bitclock and data signal is ok they sync within a reasonable range,
but mclk and data is not sync within a reasonable range, according to the pcm1794 datasheet, mclk is used by the DAC for it's internal digital interpolation filter. (other dac chip should be the same...)
The problem become... Does the internal digital interpolation filter need a mclk and data sync at the rising edge for better sound
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Old 28th August 2012, 02:59 PM   #8
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Quote:
Originally Posted by wizard1238 View Post
Does the internal digital interpolation filter need a mclk and data sync at the rising edge for better sound
From a technical point of view I doubt it. I mean we may have endless debates on subjective vs objective based design/balancing/tweaking, but one things for sure, most IC designers can never be accused of lacking in the latter. If having the master clock synchronous to the others would help on a technical level in terms of improving any of the standard performance parameters then it would be mentioned.

I mean it's obvious that the other three lines need to be synchronous as they are responsible for the data transfer and it's also obvious that any timing errors on said lines will affect how the data is clocked into the device, but in data terms the master clock has no direct link to the data. I mean DSPs and some older DACs don't even need the master clock, so from a data manipulation point of view it is completely unnecessary.
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Old 1st September 2012, 03:13 PM   #9
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Quote:
Originally Posted by wizard1238 View Post
bitclock and data signal is ok they sync within a reasonable range,
Could You check JUST!! BitClock on Your XMOS board, with the same scope set-up as mine !!
And send me the screens.on PM ....Please.

Rosendorfer
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Old 1st September 2012, 08:06 PM   #10
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The PCM1794 does not require a specific phase relationship between the SCK (also called MCK and MCLK above). But the SCK must of course be frequency locked to the bit clock etc. of the I2S signals. Actually the data sheet specifically states: "The PCM1794A requires the synchronization of LRCK and the system clock, but does not need a specific phase relation between LRCK and the system clock."

I think this is the normal situation with converters. The MCLK does not have to be phase locked, only frequency locked.
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