dac I/V convertion with very low distortion

[smms73]

And here is the circuit of the buffer with a fet at the input the distortion is very low (0.000008at 4 Volts p-p ) mainly 2º harmonic , at 16 Volts p-p the distortion is 0.000033% with a 10k load.

R13, C2 is essencial for the circuit , do not omit them.

this buffer can be use with all of the circuits post here

[smms73]

If for some reason you guys dont share my passion by the cfp

here is a boring buffer with a fet, the distortion with 4 V p-p is 0.00057% 10khz, 10k load, but it has a good harmonic profile with maily 2º harmonic and the 3ª at -140db

[jcx]

CFP and bootstrapped cascode - both raise the order of the system, may have unobvious feedback, problems at RF frequencies where device, interconnect unmodeled parasitics, coupling are important

while spice sims can in principle be augmented with models for the parasitics it is not cookbook, sometimes you just have to resort to hardware, stoppers, Zobels, lossy ferrite and a really fast 'scope (with a learning curve on how to probe for 100 MHz parasitic oscillation too)

[smms73]

thanks jcx .That is also my experience. I will talk more about this later, as I think is very important.

[keantoken]

Sergio, why not use a signal generator to probe the AC response directly and identify problems in the real prototype that way? You may stop oscillation, but this doesn't mean the device is free of peaking and step response anomalies.

I ordered a bunch of ferrite beads a while back which have been sitting in a bin. These can be quite helpful. I wish I had tried them out sooner. They're easy to test on a prototype and instantly reusable. Like any reactive component, you have to know how to use them, but they can make you work less for the same result

[zenelectro]

Originally Posted by smms73

If for some reason you guys dont share my passion by the cfp

here is a boring buffer with a fet, the distortion with 4 V p-p is 0.00057% 10khz, 10k load, but it has a good harmonic profile with maily 2º harmonic and the 3ª at -140db

smms,

With very low source resistance drive, It's not too hard to bottom out
Ltspice's distortion analyzer, ie; zero distortion.

I recommend using various drive impedances from a few hundred ohms to 10k
at 20kHz freq. This will quickly reveal real HF linearity. It will also make the
buffer more suitable for low current DAC's such as 1704 which are going to
invariably have a high(ish) OP impedance / load R. Same goes for load, go
for good linearity driving 1k.

I always do my sims at highest source impedance, 20kHz, lowest (1k/600R)
OP loading. If you can get very good linearity in these conditions you know
it's a decent design.

T

[keantoken]

Also, try an inductive source impedance, from several hundred nH's to hundreds of uH's. R13/C2 looks potentially problematic and may make it prone to oscillation with inductive source impedance. This can usually be fixed with an input shorting cap, but point is to be aware of the issue so that you know what is going wrong and why in case of problems.

[smms73]

Thanks kean and zen for the suggestions .

I have try the cascoded cfp with 25k input impedance 30Khz 4volts p-p, and the distortion was 0.00003% with a 10k load.
With 2k load the distortion is 0.0002% . with 1k load the distortion is 0.0013% . I dont recomend use this type of buffers with less than 5k ohms loads , is better to use a push-pull at that low loads.

The parasitic capacitances of the input jfet create distortion when drived by a high input impedance source. But using a bootrapped cascode insures that there is no voltage variations in this non linear capacitances. Without the cascode the distortion with such a high input impedance would be much higher.

At 25k input impedance reveal that C1 is problematic, and is better to not use it.

I have not yet evoluate this buffer design and I have not make a prototype of it yet , but when i have a spare time i will do that, the type of buffer that i use is a bjt cascoded diamond, very low distortion with low load , but is more complex than this.

keep in mind that the schematics that I post are usually ideas, and need to be further evoluated , especially for stability. That is the case of this buffers.
From now one i will include a note of warning in the schematics that i post.

[smms73]

This is an example of the method i use to look for stability problems. In real life pcb traces are not perfect connections, they have inductance. So I put small inductances in the connections between components .
Also do not use perfect capacitors in simulations , use serie inductance and serie resistance in capacitor proprieties.
Adding this inductances make a lot of difference , and the simulation more like in real life.
As I said a simulation is as good as the models we use, that include the traces between the components.
I then simulate with fast rise and fall square waves, and sine.

But of course building a prototype is a must.

This picture is from the evolution of the tagus-ess ,
This is a very stable design, the loop create by the hawkesford connection is the one that deserves more attention, I have lost many hours with this design and i think it does not have loose ends.

this picture is only an example, not a functional schematic.

[smms73]

Originally Posted by MiiB

Line stage looks really good, open-loop and with the possibility of an truly non degrading volume-control...

Non degrading volume control
Michael, can you tell me why ?