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Old 6th December 2012, 02:06 PM   #731
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Quote:
Originally Posted by smms73 View Post
No Joachim is not current dumper .
Is a amplifier in class A that has a floating power supply , and a amplifier in class AB that the only function is keep the midle of the power supply of class A amplifier equal to input signal, Both amplifiers have unitary voltage gain.
maybe this picture is more clear.
Hi, Sergio,

This is an interesting concept. However, I'm not seeing any return path in that simplified diagram for signal current which must pass through the load. While the high current 1.8V supplies (V1 and V2) are floating, the load is grounded at one end. It seems that there is no return path for load current back to the high current 1.8V floating supplies. Snce this is apparently adapted from a text book, I'll assume I have missed something.
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Last edited by Ken Newton; 6th December 2012 at 02:36 PM.
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Old 6th December 2012, 06:32 PM   #732
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The current for the load comes from the fixed power supply V3, V4 that are grounded , then it passes by the class ab amplifier then V1, V2 and next the output transistors and then it returns to ground by the load.
Another image , can you see it now?
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Old 6th December 2012, 08:04 PM   #733
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Originally Posted by smms73 View Post
The current for the load comes from the fixed power supply V3, V4 that are grounded , then it passes by the class ab amplifier then V1, V2 and next the output transistors and then it returns to ground by the load.
Another image , can you see it now?
Okay, so, the load current conducts through both V1 and V3 for the signal positive half cycle, and V2 and V4 for the signal negative half cycle. While V3 and V4 have the maximum supply voltage across them, they only supply significant current as the signal requires it, but not for the class-A bias current. Meanwhile, V1 and V2 supply the heavy class-A bias current to the output stage, but have only the minimum supply voltage across them. Do I have this correct?
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Old 6th December 2012, 09:44 PM   #734
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Yes Ken , is correct.

in my case I am thinking in using 10 Amperes bias current across the output mosfet but as I only use 1.8 volts for biasing each output mosfet the power loss in the output stage will be 18 wats per mosfet or 72 wats in total , In a pure class A design with a +75V, -75V the power loss would be 3000 wats .

The 1,8v will be achieve by using a step-down DC to DC converter runing at 300Khz.
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Old 6th December 2012, 09:51 PM   #735
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no problem, look forward to it. I suppose all efforts would need to be made to keep traces/wires the same length to avoid smearing?
The important is that all wires go to a common point, at this current level the length of the cables is not that important , but it is not dificult to make them the same size.
Only need some wires connected like this , is not a big deal.
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Old 14th December 2012, 03:28 PM   #736
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Here's something silly I came up with today. THD at full tilt of 7mA is something like 1 x 10^-5 give or take. The thing is, if the quiescent current in the output stage is 10 times or more than the silly -6.2mA of bias, then the fact that the output stage is knocked off balance doesn't matter that much for THD. Obviously, it performs even better with no DC offset current.
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Old 14th December 2012, 04:02 PM   #737
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That is a diamond triplet. Could also work as a power buffer.
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Old 14th December 2012, 04:12 PM   #738
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You could bootstrap the collectors of the input transistors to the emitters of T3, T4.
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Old 14th December 2012, 05:13 PM   #739
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Originally Posted by Joachim Gerhard View Post
You could bootstrap the collectors of the input transistors to the emitters of T3, T4.
I realize that is a normal technique, but my simulations show that it does not reduce distortion or anything good at all. I don't see the point of doing it. That's why I tie them to the rails instead. I do what makes sense to me.
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Old 14th December 2012, 06:50 PM   #740
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Try a CCS instead of the zeners.
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